Integrated Device Technology, Inc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MARCH 1996

©1996 Integrated Device Technology, Inc.

DSC-2809/6

7.4

1

4K x 36 BiCMOS

SYNCHRONOUS DUAL-PORT

STATIC RAM MODULE

IDT7M1024

IDT7099

4K x 9

IDT7099

4K x 9

IDT7099

4K x 9

IDT7099

4K x 9

L_ R/

R_ R/

L_ R/

R_ R/

R_ R/

L_ R/

L_

R_

L_

R_

R_CLK

L_CLK

L_ R/

L_

R_

R_ R/

2809 drw 01

L_

L_

R_

R_

L_

R_

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

• High-density 4K x 36 Synchronous Dual-Port SRAM

module

• Architecture based on Dual-Port RAM cells

— Allows full simultaneous access from both ports

• Synchronous operation

— 4ns set-up to clock, 1ns hold on all control, data, and

address inputs

— Data input, address, and control registers

— Fast 20ns clock to data out

— Self-timed write allows fast write cycle

• Clock enable feature

• Single 5V (

±10%) power supply

• Multiple GND pins and decoupling capacitors for maxi-

mum noise immunity

• Inputs/outputs directly TTL-compatible

DESCRIPTION:

The IDT7M1024 is a 4K x 36 bit high-speed synchronous

Dual-Port Static RAM module constructed on a co-fired ce-

ramic substrate using four IDT7099 (4K x 9) Dual-Port RAMs.

The IDT7M1024 module is designed to be used as a stand-

alone 36-bit Dual-Port Static RAM.

The IDT7M1024 provides a true synchronous Dual-Port

Static RAM interface. Registered inputs provide very short

set-up and hold times on address, data, and all critical control

inputs. All internal registers are clocked on the rising edge of

the clock signal. An asynchronous output enable is provided

to ease asynchronous bus interfacing.

The internal write pulse width is independent of the HIGH

and LOW periods of the clock. This allows the shortest

possible realized cycle times. Clock enable inputs are pro-

vided to stall the operation of the address and data input

registers without introducing clock skew for very fast inter-

leaved memory applications.

The data inputs are gated to control on-chip noise in bussed

applications. The user must guarantee that the R/

W pins are

LOW for at least one clock cycle before any write is attempted.

A HIGH on the

CE input for one clock cycle will power down the

internal circuitry to reduce static power consumption.

The IDT7M1024 module is packaged in a 142-lead ceramic