IDT7M1002

16K x 32 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.02

7

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CS

CS

CS

CS

2795 drw 07

CS

OE

ADDRESS

OW

t

(9)

(4)

(4)

DATA VALID

R/

W

(9)

2795 drw 08

R/

W

CS

ADDRESS

DATA VALID

NOTES:

1. R/

W must be HIGH during all address transitions.

CS and a LOW R/W.

CS or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must be applied.

5. If the

CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state.

6. Timing depends on which enable signal is asserted last.

7. Timing depends on which enable signal is de-asserted first.

8. If

OE is HIGH during an R/W controlled write cycle, this requirement does

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/

W

W

W

W