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IDT79R4640 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT79R4640
Description  Low-Cost Embedded 64-bit RISController w/ DSP Capability
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT79R4640 Datasheet(HTML) 6 Page - Integrated Device Technology

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April 10, 2001
IDT79RC4640™
tents will be updated, and the cache line marked for later write-
back. If the cache lookup misses, the target line is first brought
into the cache before the cache is updated.
x
Write-through with write allocate.
Loads and instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the cache con-
tents will be updated and main memory will also be written; the
state of the “writeback” bit of the cache line will be unchanged. If
the cache lookup misses, the target line is first brought into the
cache before the cache is updated.
x
Write-through without write-allocate.
Loads and instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the cache con-
tents will be updated, and the cache line marked for later write-
back. If the cache lookup misses, then only main memory is
written.
Associated with the Data Cache is the store buffer. When the
RC4640 executes a Store instruction, this single-entry buffer gets written
with the store data while the tag comparison is performed. If the tag
matches, then the data is written into the Data Cache in the next cycle
that the Data Cache is not accessed (the next non-load cycle). The store
buffer allows the RC4640 to execute a store every processor cycle and
to perform back-to-back stores without penalty.
Write Buffer
Write Buffer
Write Buffer
Write Buffer
Writes to external memory, whether cache miss writebacks or stores
to uncached or write-through addresses, use the on-chip write buffer.
The write buffer holds up to four address and data pairs. The entire
buffer is used for a data cache writeback and allows the processor to
proceed in parallel with memory update.
System Interface
System Interface
System Interface
System Interface
The RC4640 supports a 32-bit system interface that is syntactically
compatible with the RC4700 system interface.
The interface consists of a 32-bit Address/Data bus with eight check
bits and a 9-bit command bus protected with parity. In addition, there are
eight handshake signals and six interrupt inputs. The interface has a
simple timing specification and is capable of transferring data between
the processor and memory at a peak rate of 500MB/sec at 125MHz on
the bus.
Figure 2 on page 7 shows a typical system using the RC4640. In this
example two banks of DRAMs are used to supply and accept data with a
DDxxDD data pattern.
The RC4640 clocking interface allows the CPU to be easily mated
with external reference clocks. The CPU input clock is the bus reference
clock, and can be between 50 and 125MHz (somewhat dependent on
maximum pipeline speed for the CPU).
An on-chip phase-locked-loop generates the pipeline clock from the
system interface clock by multiplying it up an amount selected at system
reset. Supported multipliers are values 2 through 8 inclusive, allowing
systems to implement pipeline clocks at significantly higher frequency
than the system interface clock.
System Address/Data Bus
System Address/Data Bus
System Address/Data Bus
System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to transfer
addresses and data between the RC4640 and the rest of the system. It
is protected with an 8-bit parity check bus, SysADC. When initialized for
32-bit operation, SysAD can be viewed as a 32-bit multiplexed bus, with
4 parity check bits.
The system interface is configurable to allow easier interfacing to
memory and I/O systems of varying frequencies. The bus frequency and
reference timing of the RC4640 are taken from the input clock. The rate
at which the CPU transmits data to the system interface is program-
mable via boot time mode control bits. The rate at which the processor
receives data is fully controlled by the external device. Therefore, either
a low cost interface requiring no read or write buffering or a faster, high
performance interface can be designed to communicate with the
RC4640. Again, the system designer has the flexibility to make these
price/performance trade-offs.
System Command Bus
System Command Bus
System Command Bus
System Command Bus
The RC4640 interface has a 9-bit System Command (SysCmd) bus.
The command bus indicates whether the SysAD bus carries an address
or data. If the SysAD carries an address, then the SysCmd bus also
indicates what type of transaction is to take place (for example, a read
or write). If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data word trans-
mitted, or the cache state of this data line is clean exclusive). The
SysCmd bus is bidirectional to support both processor requests and
external requests to the RC4640. Processor requests are initiated by
the RC4640 and responded to by an external device. External requests
are issued by an external device and require the RC4640 to respond.
The RC4640 supports single datum (one to eight byte) and 8-word
block transfers on the SysAD bus. In the case of a single-datum
transfer, the low-order 3 address bits gives the byte address of the
transfer, and the SysCmd bus indicates the number of bytes being
transferred.
Handshake Signals
Handshake Signals
Handshake Signals
Handshake Signals
There are six handshake signals on the system interface. Two of
these, RdRdy* and WrRdy* are used by an external device to indicate to
the RC4640 whether it can accept a new read or write transaction. The
RC4640 samples these signals before deasserting the address on read
and write requests.
The following is a list of the supported external requests:
x
Read Response
x
Null


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