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IDT79R4640 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT79R4640
Description  Low-Cost Embedded 64-bit RISController w/ DSP Capability
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT79R4640 Datasheet(HTML) 2 Page - Integrated Device Technology

 
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April 10, 2001
IDT79RC4640™
Description
Description
Description
Description
The IDT79RC4640 is a low-cost member of the Integrated Device
Technology, Inc. RC4000 family, targeted to a variety of performance-
hungry embedded applications. The RC4640 continues the RC4000
tradition of high-performance through high-speed pipelines, high-band-
width caches and bus interface, 64-bit architecture, and careful attention
to efficient control. The cost of this performance is reduced by removing
functional units frequently not required for many embedded applications.
The RC4640 supports a wide variety of embedded processor-based
applications, such as internetworking equipment (routers, switches),
office automation equipment (printers, scanners), and consumer multi-
media game systems. Also, being upwardly software-compatible with
the RC32300 family as well as bus- and upwardly software-compatible
with the IDT RC4000 family, the RC4640 will serve in many of the same
applications. And, the RC4640 supports applications that require integer
digital signal processing (DSP) functions.
The RC64475 and RC64575 processors offer a direct migration path
for designs based on IDT’s RC4650 processors, through full pin and
socket compatibility.
The RC4640 brings 64-bit performance levels to lower cost systems.
High performance is preserved by retaining large on-chip two-way set-
associative caches, a streamlined high-speed pipeline, high bandwidth,
64-bit execution, and facilities such as early restart for data cache
misses.
These techniques allow the system designer over 3.2 GB/sec aggre-
gate internal bandwidth, 500 MB/sec bus bandwidth, almost 352 Dhrys-
tone MIPS, 89MFlops, and 133.5 M Mul-Add/sec. An array of tools
facilitates rapid development of RC4640-based systems, allowing a
wide variety of customers access to the processor’s high-performance
capabilities while maintaining short time-to-market goals.
Hardware Overview
Hardware Overview
Hardware Overview
Hardware Overview
Some key elements of the RC4640 are briefly described below. More
detailed information is available in the IDT79RC4640/IDT79RC4650
RISC Processor Hardware User’s Manual.
Pipeline
Pipeline
Pipeline
Pipeline
The RC4640 uses a 5-stage pipeline that is similar to the
IDT79RC3000 and the IDT79RC4700 processors. The simplicity of this
pipeline allows the RC4640 to cost less than super-scalar processors
and require less power than super-pipelined processors. So, unlike
superscalar processors, applications that have large data dependen-
cies, or require frequent load/stores, can still achieve peak performance.
Integer Execution Engine
Integer Execution Engine
Integer Execution Engine
Integer Execution Engine
The RC4640 implements the MIPS-III Instruction Set Architecture
and is fully upward compatible with applications that run on earlier
generation parts. The RC4640 is software-compatible with the RC4650,
and includes the instruction set found in the RC4700 microprocessor,
targeted at higher performance while maintaining binary compatibility
with RC32300 processors.
The extensions result in better code density, greater multi-
processing support, improved performance for commonly used code
sequences in operating system kernels, and faster execution of floating-
point intensive applications. All resource dependencies are made trans-
parent to the programmer, insuring transportability among implementa-
tions of the MIPS instruction set architecture. In addition, MIPS-III
specifies new instructions defined to take advantage of the 64-bit archi-
tecture of the processor.
Finally, the RC4640 also implements additional instructions, which
are considered extensions to the MIPS-III architecture. These instruc-
tions improve the multiply and multiply-add throughput of the CPU,
making it well suited to a wide variety of imaging and DSP applications.
These extensions, which use opcodes allocated by MIPS Technologies
for this purpose, are supported by a wide variety of development tools.
The MIPS integer unit implements a load/store architecture with
single cycle ALU operations (logical, shift, add, sub) and autonomous
multiply/divide unit. The 64-bit register resources include: 32 general-
purpose orthogonal integer registers, the HI/LO result registers for the
integer multiply/divide unit, and the program counter. In addition, the on-
chip floating-point co-processor adds 32 floating-point registers, and a
floating-point control/status register.
Register File
Register File
Register File
Register File
The RC4640 has 32 general-purpose 64-bit registers. These regis-
ters are used for scalar integer operations and address calculation. The
register file consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
Arithmetic Logic Unit
Arithmetic Logic Unit
Arithmetic Logic Unit
Arithmetic Logic Unit
The RC4640 ALU consists of the integer adder and logic unit. The
adder performs address calculations in addition to arithmetic operations;
the logic unit performs all of the logic and shift operations. Each unit is
highly optimized and can perform an operation in a single pipeline cycle.
Integer Multiply/Divide
Integer Multiply/Divide
Integer Multiply/Divide
Integer Multiply/Divide
The RC4640 uses a dedicated integer multiply/divide unit, optimized
for high-speed multiply and multiply-accumulate operation. Table 1
shows the performance, expressed in terms of pipeline clocks, achieved
by the RC4640 integer multiply unit.
Opcode
Operand
Size
Latency Repeat Stall
MULT/U, MAD/U
16 bit
3
2
0
32 bit
4
3
0
MUL
16 bit
3
2
1
32 bit
4
3
2
DMULT, DMULTU
any
6
5
0
DIV, DIVU
any
36
36
0
DDIV, DDIVU
any
68
68
0
Table 1 RC4640 Integer Multiply Operation


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