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IDT77155 Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT77155
Description  PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT77155 Datasheet(HTML) 1 Page - Integrated Device Technology

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COMMERCIAL TEMPERATURE RANGE
NOVEMBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2066/5
8.03
1
• Supports up to 4 PHYs for Multi-PHY connections with 2-
bit address and 8-bit data using UTOPIA 2 protocol.
• Provides an 8-bit microprocessor bus interface for
configuration, control and monitoring.
• Low power CMOS
• 128 pin PQFP Package (14 mm x 20 mm).
DESCRIPTION
The IDT77155 is a member of IDT's SWITCHStARfamily
of products for Asynchronous Transfer Mode (ATM) net-
works.
The IDT77155 is a integrated circuit that provides the
SONET/SDH processing and ATM mapping functions of a
155 Mbps/51 Mbps ATM User Network Interface. Provides full
compliance with SONET/SDH requirements and ATM Forum
Integrated Device Technology, Inc.
NICStAR is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
PHY (TC-PMD) USER NETWORK
INTERFACE FOR 155 MBPS ATM
NETWORK APPLICATIONS
ADVANCED
INFORMATION
IDT77155
KEY FEATURES
• One chip ATM User Network Interface for 155.52 Mbps/
51.84Mbps operating speed.
• Full implementation of the SONET/SDH criteria according
to Bellcore GR-253-CORE and ITU-T G.709, G.783.
• Full implementation of the ATM physical layer according
to CCITT I.432 and ATM Forum User Network Interface
Specification.
• Full-duplex 155.52 Mbps STS-3c/STM-1 or 51.84 Mbps
STS-1 data with built-in clock/data recovery and clock
synthesis.
• Supports 4-cell PHY FIFO buffers for both transmit and
receive directions with parity.
• Provides GFC bits insertion and extraction.
• UTOPIA Level 1 and Level 2 Interface.
SYSTEM-LEVEL FUNCTIONAL BLOCK DIAGRAM
Parallel
to
Serial
Transmit
SONET
Framer
Clk Gen.
Serial
to
Parallel
Receive
SONET
Framer
Decoder
Receive
UTOPIA
Cell
FIFO
Encoder
Clk Rec.
RRCLK+
RRCLK-
ALOS+
ALOS-
RXD+
RXD-
RXDO+
RXDO-
RCA
TxADDR[1:0]
TRCLK+
TRCLK-
TXD+
TXD-
TXC+
TXC-
Transmit
UTOPIA
Cell
FIFO
MPHYEN
TCA
TSOC
TDAT[7:0]
TXPRTY
TFCLK
RSOC
RDAT[7:0]
RXPRTY
RFCLK
TSEN
RxADDR[1:0]
3497 drw 01
Micoprocessor
Interface


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