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IDT74FCT833BE Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT74FCT833BE Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 8 page IDT54/74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES 7.21 3 FUNCTION TABLE (2) Inputs Outputs TI Incl Parity OE OET OE OER CLR CLR CLK RI ( ∑ or H’s) ( ∑ of H’s) RI TI Parity ERR ERR (1) Function LH H ↑ H (Odd) NA NA H L H Transmit data from R Port LH H ↑ H (Even) NA NA H H L to T Port with parity; LH H ↑ L (Odd) NA NA L L H receiving path is disabled. LH H ↑ L (Even) NA NA L H L HL H ↑ NA H (Odd) H NA NA H Receive data from T Port HL H ↑ NA H (Even) H NA NA L to R Port with parity test HL H ↑ NA L (Odd) L NA NA H resulting in flag: HL H ↑ NA L (Even) L NA NA L transmitting path is disabled. — — L — — — NA NA NA H Clear the state of error flag register. H H H H or L — — Z Z Z * Both transmitting and H H L — — — Z Z Z H receiving paths are disabled. HH H ↑ H or L (Odd) — Z Z Z H Parity logic defaults to HH H ↑ H or L (Even) — Z Z Z L transmit mode. LL H ↑ H (Odd) NA NA H H L Forced-error checking. LL H ↑ H (Even) NA NA H L H LL H ↑ L (Odd) NA NA L H L LL H ↑ L (Even) NA NA L L H NOTES: 2557 tbl 03 1. Output state assumes HIGH output pre-state. 2. H = HIGH Z = High Impedance Odd = Odd number of logic one’s L = LOW NA = Not Applicable Even = Even number of logic one’s ↑ = LOW-to-HIGH transition of clock – = Don’t Care or Irrelevant I = 0, 1, 2, 3, 4, 5, 6, 7 *No change to stored Error State |
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