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IDT74FCT273CTL Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT74FCT273CTL Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 7 page Integrated Device Technology, Inc. FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET IDT54/74FCT273T/AT/CT DESCRIPTION: The IDT54/74FCT273T/AT/CT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT273T/AT/CT have eight edge-triggered D-type flip- flops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset ( MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s O output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. PIN CONFIGURATIONS INDEX D1 O1 O2 D2 D3 D7 D6 O6 O5 D5 LCC TOP VIEW 3 2 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10111213 L20-2 2568 drw 01 2568 drw 02 FUNCTIONAL BLOCK DIAGRAM D CP RD Q D CP RD Q O0 O1 O2 O3 O4 O5 O6 O7 CP MR D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D CP RD Q D0 D1 D2 D3 D4 D5 D6 D7 2568 drw 03 MILITARY AND COMMERCIAL TEMPERATURE RANGES APRIL 1995 ©1995 Integrated Device Technology, Inc. 6.10 DSC-4209/3 1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEATURES: • Std., A, and C speed grades • Low input and output leakage ≤1µA (max.) • CMOS power levels • True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Product available in Radiation Tolerant and Radiation Enhanced versions • Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) • Available in DIP, SOIC, QSOP, CERPACK and LCC packages MR O0 D0 D1 O1 O2 D2 D3 O3 GND O7 D7 D6 O6 O5 D4 D5 O4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DIP/SOIC/QSOP/CERPACK TOP VIEW P20-1 D20-1 SO20-2 SO20-8 & E20-1 CP |
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