IDT74FCT3932-100, IDT74FCT32932-100

LOW SKEW PLL-BASED CMOS CLOCK DRIVER

COMMERCIAL TEMPERATURE RANGES

9.9

6

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

(7)

GENERAL AC SPECIFICATION NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested.

3. These specifications are guaranteed but not production tested.

4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.

6. The tPD spec gives the limits of the phase offset between the REF_IN input and the Q_FB output.

7. The AC specifications are only guaranteed with the decoupling scheme shown in figure 2.

3267 tbl 13

Feedback Output

±0.5ns

REF_IN input

Offset

3267 drw 03

Symbol

Parameter

Max.

Unit

REF_IN-Q_FB

Propagation Delay

(REF_IN input to Q outputs)

No Load

–0.5

+0.5

ns

Rise/Fall Time (between 0.8 and 2.0V)

FCT3932

0.5

1.5

ns

All Outputs

FCT32932

0.5

2.0

Output Duty Cycle

45

55

%

Output to Output Skew (All outputs at

same frequency rising edge)

—

500

ps

Output to Output Skew (All outputs at

same frequency falling edge)

—

500

ps

Output to Output Skew (All outputs,

rising edge any frequency)

—

1.0

ns

Time required to acquire

Phase-Lock from time

REF_IN input signal is received

110

ms

Output Enable Time

OEx

(LOW-to-HIGH) to Q

3.0

8.0

ns

Output Disable Time

OEx

(HIGH-to-LOW) to Q

3.0

8.0

ns