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IDT54FCT3574 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT54FCT3574 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 7 page Integrated Device Technology, Inc. DESCRIPTION: The FCT3574/A are 8-bit registers built using an advanced dual metal CMOS technology. These registers consist of eight D-type flip-flops with a buffered common clock and buffered 3-state output control. When the output ( OE) input is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the high-impedance state. Input data meeting the set-up and hold time requirements of the D inputs is transferred to the O outputs on the LOW-to- HIGH transition of the clock input. IDT54/74FCT3574/A ADVANCE INFORMATION 3.3V CMOS OCTAL D REGISTERS (3-STATE) The IDT logo is a registered trademark of Integrated Device Technology, Inc. 1 FEATURES: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • 25 mil Center SSOP Packages • Extended commercial range of -40 °C to +85°C •VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4 µW typ. static) • Rail-to-Rail output swing for increased noise margin • Military product compliant to MIL-STD-883, Class B FUNCTIONAL BLOCK DIAGRAM D0 O0 D1 O1 D2 O2 D3 O3 D4 O4 D5 O5 D6 O6 D7 O7 CP OE D Q CP D CP D CP D CP D CP D CP D CP D CP 3095 drw 01 QQQ Q Q QQ PIN CONFIGURATION OE D0 D1 D2 D3 D4 D5 D6 D7 GND O0 O1 O2 O3 O4 O6 CP O5 O7 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DIP/SOIC/SSOP TOP VIEW P20-1 D20-1 SO20-2 & SO20-7 3095 drw 02 PIN DESCRIPTION 3095 tbl 01 Pin Names Description DN D flip-flop data inputs CP Clock Pulse for the register. Enters data on LOW-to-HIGH transition. ON 3-state outputs, (true) ON 3-state outputs, (inverted) OE Active LOW 3-state Output Enable input MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995 ©1995 Integrated Device Technology, Inc. 8.14 DSC-4650/- |
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