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IDT74FCT16373CTPV Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT74FCT16373CTPV Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 8 page 5.7 6 IDT54/74FCT16373T/AT/CT/ET, 162373T/AT/CT/ET FAST CMOS 16-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT16373T/162373T FCT16373AT/162373AT Com'l. Mil. Com'l. Mil. Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit tPLH tPHL Propagation Delay xDx to xOx CL = 50pF RL = 500 Ω 1.5 8.0 1.5 8.5 1.5 5.2 1.5 5.6 ns tPLH tPHL Propagation Delay xLE to xOx 2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 ns tPZH tPZL Output Enable Time 1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 ns tPHZ tPLZ Output Disable Time 1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 ns tSU Set-up Time HIGH or LOW, xDx to xLE 2.0 — 2.0 — 2.0 — 2.0 — ns tH Hold Time HIGH or LOW, xDx to xLE 1.5 — 1.5 — 1.5 — 1.5 — ns tW xLE Pulse Width HIGH 6.0 — 6.0 — 5.0 — 6.0 — ns tSK(o) Output Skew(3) — 0.5 — 0.5 — 0.5 — 0.5 ns 2543 tbl 09 FCT16373CT/162373CT FCT16373ET/162373ET Com'l. Mil. Com'l. Mil. Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit tPLH tPHL Propagation Delay xDx to xOx CL = 50pF RL = 500 Ω 1.5 4.2 1.5 5.1 1.5 3.4 — — ns tPLH tPHL Propagation Delay xLE to xOx 2.0 5.5 2.0 8.0 1.5 3.7 — — ns tPZH tPZL Output Enable Time 1.5 5.5 1.5 6.3 1.5 4.4 — — ns tPHZ tPLZ Output Disable Time 1.5 5.0 1.5 5.9 1.5 3.6 — — ns tSU Set-up Time HIGH or LOW, xDx to xLE 2.0 — 2.0 — 1.0 — — — ns tH Hold Time HIGH or LOW, xDx to xLE 1.5 — 1.5 — 1.0 — — — ns tW xLE Pulse Width HIGH 5.0 — 6.0 — 3.0(4) ——— ns tSK(o) Output Skew(3) — 0.5 — 0.5 — 0.5 — — ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested. |
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