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IDT74FCT273T Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT74FCT273T
Description  FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74FCT273T Datasheet(HTML) 2 Page - Integrated Device Technology

   
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
6.10
2
PIN DESCRIPTION
FUNCTION TABLE
(1)
NOTE:
2568 tbl 02
1. H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑ = LOW-to-HIGH Clock Transition
ABSOLUTE MAXIMUM RATINGS
(1)
CAPACITANCE (TA = +25
°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
CIN
Input
Capacitance
VIN = 0V
6
10
pF
COUT
Output
Capacitance
VOUT = 0V
8
12
pF
Symbol
Rating
Commercial
Military
Unit
VTERM(2) Terminal Voltage
with Respect to
GND
–0.5 to +7.0
–0.5 to +7.0
V
VTERM(3) Terminal Voltage
with Respect to
GND
–0.5 to
VCC +0.5
–0.5 to
VCC +0.5
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
PT
Power Dissipation
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120
–60 to +120
mA
2568 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
NOTE:
1. This parameter is measured at characterization but not tested.
2568 lnk 04
Inputs
Outputs
Operating Mode
MR
MR
CP
DN
ON
Reset (Clear)
L
X
X
L
Load "1"
H
hH
Load "0"
H
IL
2568 tbl 01
Pin Names
Description
DN
Data Inputs
MR
Master Reset (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
ON
Data Outputs


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