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IDT74FCT273 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT74FCT273
Description  FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74FCT273 Datasheet(HTML) 1 Page - Integrated Device Technology

   
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Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
©1992 Integrated Device Technology, Inc.
7.10
DSC-4609/2
®
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET
FEATURES:
• IDT54/74FCT273 equivalent to FAST
™ speed;
• IDT54/74FCT273A 45% faster than FAST
• IDT54/74FCT273C 55% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
•IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5
µA max.)
• Octal D flip-flop with Master Reset
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology.
The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
with individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset (
MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the
MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
FUNCTIONAL BLOCK DIAGRAM
2558 drw 01
D
O7
CP
Q
D7
D
O6
CP
Q
D6
D
O5
CP
Q
D5
D
O4
CP
Q
D4
D
O3
CP
Q
D3
D
O2
CP
Q
D2
D
O1
CP
Q
D1
D
O0
CP
Q
D0
MR
CP
RD
RD
RD
RD
RD
RD
RD
RD
PIN CONFIGURATIONS
5
6
7
8
9
10
D0
D1
O1
1
2
3
4
20
19
18
17
16
15
14
13
Vcc
12
11
MR
D7
O2
D2
D3
O3
CP
D6
O6
O5
D5
D4
GND
O4
O0
O7
P20-1
D20-1
SO20-2
&
E20-1
2558 drw 02
INDEX
15
14
18
17
16
5
6
7
8
4
L20-2
D1
O1
D7
O2
D2
D3
D6
O6
O5
D5
9 10 11 12 13
32
1
20 19
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
DIP/SOIC/CERPACK
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