6.42

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

11

NOTES:

2.

3. Multiple bytes may be selected during the same cycle.

NOTES:

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

Operation

GW

BWE

Read

H

H

X

XXX

Read

H

L

HHHH

Write all Bytes

L

XX

XXX

Write all Bytes

H

LLLLL

Write Byte 1

(3)

H

L

L

HHH

Write Byte 2

(3)

HL

H

L

H

H

Write Byte 3

(3)

HL

H

H

L

H

Write Byte 4

(3)

H

L

HHH

L

5301 tbl 12

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

0

0

1

1

0

1

1

Second Address

0

1

1

0

1

1

0

0

Third Address

1

0

1

1

0

0

0

1

Fourth Address

(1)

11

00

0

1

1

0

5301 tbl 15

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

A1

A0

A1

A0

A1

A0

First Address

0

0

0

1

1

0

1

1

Second Address

0

1

0

0

1

1

1

0

Third Address

1

0

1

1

0

0

0

1

Fourth Address

(1)

11

1

0

0

1

0

0

5301 tbl 14

Operation

(2)

OE

ZZ

I/O Status

Power

Read

L

L

Data Out

Active

Read

H

L

High-Z

Active

Write

X

L

High-Z – Data In

Active

Deselected

X

L

High-Z

Standby

Sleep Mode

X

H

High-Z

Sleep

5301 tbl 13