Integrated Device Technology, Inc.

FEATURES:

• 0.5 MICRON CMOS Technology

• ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

• Packages include 25 mil pitch SSOP, 19.6 mil pitch

TSSOP and 15.7 mil pitch TVSOP

• Extended commercial range of -40

°C to +85°C

±0.3V, Normal Range or

• CMOS power levels (0.4

µW typ. static)

• Rail-to-Rail output swing for increased noise margin

• Low Ground Bounce (0.3V typ.)

• Inputs (except I/O) can be driven by 3.3V or 5V

components

3.3V CMOS

16-BIT BUS TRANSCEIVER/

REGISTERS

IDT74FCT163646/A/C

1

1

1

OE

1

DIR

1

SBA

1

SAB

1

CLKBA

1

CLKAB

TO 7 OTHER CHANNELS

B REG

A REG

D

C

C

D

2

2

OE

2

DIR

2

SBA

2

SAB

2

2

CLKBA

2

CLKAB

TO 7 OTHER CHANNELS

B REG

A REG

D

C

C

D

2778 drw 01

2778 drw 02

COMMERCIAL TEMPERATURE RANGES

AUGUST 1996

8.8

1

©1996 Integrated Device Technology, Inc.

DSC-2778/6

DESCRIPTION:

The FCT163646/A/C 16-bit registered transceivers are

built using advanced dual metal CMOS technology. These

high-speed, low-power devices are organized as two inde-

pendant 8-bit bus transceivers with 3-state D-type registers.

The control circuitry is organized for multiplexed transmission

of data between A bus and B bus either directly or from the

internal storage registers.

Each 8-bit transceiver/register

features direction control (xDIR), over-riding Output Enable

control (x

OE) and Select lines (xSAB and xSBA) to select

either real-time data or stored data. Separate clock inputs are

provided for A and B port registers. Data on the A or B data

bus, or both, can be stored in the internal registers by the

LOW-to-HIGH transitions at the appropriate clock pins. Flow-

through organization of signal pins simplifies layout. All inputs

are designed with hysteresis for improved noise margin.

The FCT163646/A/C have series current limiting resistors.

This offers low ground bounce, minimal undershoot, and

controlled output fall times-reducing the need for external

series terminating resistors.

FUNCTIONAL BLOCK DIAGRAM

The IDT logo is a registered trademark of Integrated Device Technology, Inc.