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IDT54FCT162H272ET Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT54FCT162H272ET Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 8 page 5.5 3 IDT54/74FCT162H272AT/CT/ET FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES NOTES: 1. Output level before the indicated steady-state input conditions were established. 2. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance ↑ = LOW-to-HIGH Transition ABSOLUTE MAXIMUM RATINGS (1) FUNCTION TABLES (2) 3071 tbl 04 3071 tbl 05 NOTES: 1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os. PIN DESCRIPTION Signal I/O Description A(1:12) I/O Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1) 1B(1:12) I/O Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1) 2B(1:12) I/O Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1) CLK I Clock Input. CEA1B I Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked into register A-1B (Active LOW). CEA2B I Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked into register A-2B (Active LOW). CE1B I Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A (Active LOW). CE2B I Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A (Active LOW). SEL I 1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port. OEA I Synchronous Output Enable for A Port (Active LOW). OEB I Synchronous Output Enable for 1B Port and 2B Port (Active LOW). 3071 tbl 01 Inputs Output 1B 2B SEL CE1B CE1B CE2B CE2B OEA OEA CLK A HX H L X L ↑ H LX H L X L ↑ L X X HHX L ↑ A(1) XH L X L L ↑ H XL L X LL ↑ L XX L X H L ↑ A(1) X XXXXH ↑ Z Inputs Outputs A CEA1B CEA1B CEA2B CEA2B OEB OEB CLK 1B 2B HL L L ↑ HH LLL L ↑ LL HL H L ↑ HB(1) LLH L ↑ LB(1) HHL L ↑ B(1) H LH L L ↑ B(1) L XH H L ↑ B(1) B(1) XXX H ↑ ZZ XXX L ↑ Active Active Symbol Description Max. Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7.0 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC +0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +120 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specifica- tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT. 3071 tbl 02 NOTE: 1. This parameter is measured at characterization but not tested. CAPACITANCE (TA = +25 °C, F = 1.0MHZ) 3071 tbl 03 Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 3.5 6.0 pF CI/O I/O Capacitance VOUT = 0V 3.5 8.0 pF |
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