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IDT72404L15D Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72404L15D Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 9 page IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES 5.01 3 OPERATING CONDITIONS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Commercial Military and Commercial IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10 IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10 IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10 IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10 Symbol Parameters FIgure Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tSIH (1) Shift in HIGH Time 2 9 — 9 — 11 — 11 — 11 — ns tSIL Shift in LOW TIme 2 11 — 17 — 24 — 25 — 30 — ns tIDS Input Data Set-up 2 0 — 0 — 0 — 0 — 0 — ns tIDH Input Data Hold Time 2 13 — 15 — 20 — 30 — 40 — ns tSOH (1) Shift Out HIGH Time 5 9 — 9 — 11 — 11 — 11 — ns tSOL Shift Out LOW Time 5 11 — 17 — 24 — 25 — 25 — ns tMRW Master Reset Pulse 8 20 — 25 — 25 — 25 — 30 — ns tMRS Master Reset Pulse to SI 8 10 — 10 — 10 — 25 — 35 — ns tSIR Data Set-up to IR 4 3 — 3 — 5 — 5 — 5 — ns tHIR Data Hold from IR 4 13 — 15 — 20 — 30 — 30 — ns tSOR (4) Data Set-up to OR HIGH 7 0 — 0 — 0 — 0 — 0 — ns 2747 tbl 05 AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Commercial Military and Commercial IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10 IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10 IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10 IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10 Symbol Parameters FIgure Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tIN Shift In Rate 2 — 45 — 35 — 25 — 15 — 10 MHz tIRL (1) Shift In to Input Ready LOW 2 — 18 — 18 — 21 — 35 — 40 ns tIRH (1) Shift In to Input Ready HIGH 2 — 18 — 20 — 28 — 40 — 45 ns tOUT Shift Out Rate 5 — 45 — 35 — 25 — 15 — 10 MHz tORL (1) Shift Out to Output Ready LOW 5 — 18 — 18 — 19 — 35 — 40 ns tORH (1) Shift Out to Output Ready HIGH 5 — 19 — 20 — 34 — 40 — 55 ns tODH Output Data Hold (Previous Word) 5 5 — 5 — 5 — 5 — 5 — ns tODS Output Data Shift (Next Word) 5 — 19 — 20 — 34 — 40 — 55 ns tPT Data Throughput or "Fall-Through" 4, 7 — 30 — 34 — 40 — 65 — 65 ns tMRORL Master Reset to OR LOW 8 — 25 — 28 — 35 — 35 — 40 ns tMRIRH Master Reset to IR HIGH 8 — 25 — 28 — 35 — 35 — 40 ns tMRQ Master Reset to Data Output LOW 8 — 20 — 20 — 25 — 35 — 40 ns tOOE (3) Output Valid from OE LOW 9 — 12 — 15 — 20 — 30 — 35 ns tHZOE (3,4) Output High-Z from OE HIGH 9 — 12 — 12 — 15 — 25 — 30 ns tIPH (2,4) Input Ready Pulse HIGH 4 9 — 9 — 11 — 11 — 11 — ns tOPH (2,4) Ouput Ready Pulse HIGH 7 9 — 9 — 11 — 11 — 11 — ns NOTES: 2747 tbl 06 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1 µF directly between VCC and GND with very short lead length is recommended. 2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like speed grades. 3. IDT72403 and IDT72404 only. 4. Guaranteed by design but not currently tested. |
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