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IDT72V36110L10PF Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72V36110L10PF Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 36 page  2 COMMERCIAL AND INDUSTRIAL TEMPERATURERANGES IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 PIN CONFIGURATIONS TQFP (PK128-1, order code: PF) TOP VIEW DESCRIPTION: The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/ 72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In- First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits: • Flexible x36/x18/x9 Bus-Matching on both read and write ports • The period required by the retransmit operation is fixed and short. • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. • High density offerings up to 4 Mbit Bus-Matching Sync FIFOs are particularly appropriate for network, video, telecommunications,datacommunicationsandotherapplicationsthatneedto buffer large amounts of data and match busses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and Bus- Matching (BM) pin during the Master Reset cycle. TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable ( WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable ( REN)input. DataisreadfromtheFIFOoneveryrisingedge NOTE: 1. DNC = Do Not Connect. VCC OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 IW D35 D34 D33 D32 D31 VCC D30 GND D29 D28 D27 D26 D25 D24 D23 GND D22 D21 D20 D19 D18 GND D17 D16 D15 VCC D13 D12 GND D11 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 Q35 Q34 Q33 Q32 GND GND Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 GND GND Q23 Q22 Q21 Q20 Q19 Q18 GND Q17 Q16 Q15 Q14 Q13 Q12 GND Q11 Q10 INDEX WEN SEN DNC(1) D14 VCC VCC VCC VCC VCC VCC 4667 drw 02 DNC(1) |
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