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IDT72615L25PF Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT72615L25PF Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 20 page IDT72605/IDT72615 CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2 COMMERCIAL TEMPERATURE RANGE 5.18 6 AC TEST CONDITIONS In Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 2 2704 tbl 07 +5V 1.1K Ω 680 Ω 30pF* D.U.T. 2704 drw 05 AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ±10%, TA = 0°C to +70°C) Commercial 72615L20 72615L25 72615L35 72615L50 72605L20 72605L25 72605L35 72605L50 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Timing Figures fCLK Clock frequency — 50 — 40 — 28 — 20 MHz — tCLK Clock cycle time 20 — 25 — 35 — 50 — ns 4,5,6,7 tCLKH Clock HIGH time 8 — 10 — 14 — 20 — ns 4,5,6,7,12,13,14,15 tCLKL Clock LOW time 8 — 10 — 14 — 20 — ns 4,5,6,7,12,13,14,15 tRS Reset pulse width 20 — 25 — 35 — 50 — ns 3 tRSS Reset set-up time 12 — 15 — 21 — 30 — ns 3 tRSR Reset recovery time 12 — 15 — 21 — 30 — ns 3 tRSF Reset to flags in intial state — 27 — 28 — 35 — 50 ns 3 tA Data access time 3 10 3 15 3 21 3 25 ns 5,7,8,9,10,11 tCS Control signal set-up time (1) 6 — 6 — 8 — 10 — ns 4,5,6,7,8,9,10,11, 12, 13,14,15 tCH Control signal hold time (1) 1 — 1 — 1 — 1 — ns 4,5,6,7,10,11,12, 13, 14,15 tDS Data set-up time 6 — 6 — 8 — 10 — ns 4,6,8,9,10,11 tDH Data hold time 1 — 1 — 1 — 1 — ns 4,6 tOE Output Enable LOW to 3 10 3 13 3 20 3 28 ns 5,7,8,9,10,11 output data valid (2) tOLZ Output Enable LOW to data 0 — 0 — 0 — 0 — ns 5,7,8,9,10,11 bus at Low-Z (2) tOHZ Output Enable HIGH to data 3 10 3 13 3 20 3 28 ns 5,7,10,11 bus at High-Z (2) tFF Clock to Full Flag time — 10 — 15 — 21 — 30 ns 4,6,10,11 tEF Clock to Empty Flag time — 10 — 15 — 21 — 30 ns 5,7,8,9,10,11 tPAE Clock to Programmable — 12 — 15 — 21 — 30 ns 12,14 Almost Empty Flag time tPAF Clock to Programmable — 12 — 15 — 21 — 30 ns 13,15 Almost Full Flag time tSKEW1 Skew between CLKA & CLKB 10 — 12 — 17 — 20 — ns 4,5,6,7,8,9,10,11 for Empty/Full Flags (2) tSKEW2 Skew between CLKA & CLKB 17 — 19 — 25 — 34 — ns 4, 7,12,13,14,15 for Programmable Flags (2) NOTES: 1. Control signals refer to CSA, R/WA, ENA, A2, A1, A0, R/WB, ENB. 2. Minimum values are guaranteed by design. 2704 tbl 08 or equivalent circuit Figure 2. Output Load * Includes jig and scope capacitances. |
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