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IDT7210L30CB Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT7210L30CB Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 10 page 11.2 3 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES NC X15 RND CLKY TC PREL CLKP P33 X14 CLKX VCC TSX P34 NC X13 X11 X12 P30 X9 X10 X7 X8 X5 X6 X3 X4 NC NC 11 10 09 08 07 06 05 04 03 02 01 ABC D E F G H J KL Pin 1 Designator G68-2 2577 drw 05 P31 P28 P29 P26 P27 P24 P25 P22 P23 P20 P21 P18 P19 P16 P17 Y2, P2 Y4, P4 Y6, P6 Y8, P8 Y10, P10 Y12, P12 Y14, P14 Y1, P1 Y3, P3 Y5, P5 Y7, P7 Y9, P9 Y11, P11 Y13, P13 Y15, P15 X1 X2 ACC TSL SUB TSM P32 X0 Y0, P0 GND PGA TOP VIEW PIN DESCRIPTIONS 2577 tbl 01 Pin Name I/O Description X0 - 15 I Data Inputs Y0 - 15/ P0 - 15 I/O Multiplexed I/O port. Y0 - 15 are data inputs and can be used to preload LSP register on PREL = 1. P0 - 15 are LSP register outputs - enabled by TSL. P16 - 31 I/O MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1. P32 - 34 I/O XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when PREL = 1. CLKX I Input data X0 - 15 loaded in X input register on CLKX rising edge. CLKY I Input data Y0 - 15 loaded in Y input register on CLKY rising edge. CLKP I Output data loaded into output register on rising edge of CLKP. TSX I TSX = 0 enables XTP outputs, TSX = 1 tristates P32 - 34 lines. TSM I TSM = 0 enables MSP outputs, TSM = 1 tristates P16 - 31 lines. TSL I TSL = 0 enables LSP outputs, TSL = 1 tristates P0 - 15 lines. PREL I When PREL= 1 data is input on P0 - 15 lines. When PREL = 0, inputs on these lines are ignored. ACC I This input is loaded into the control register on the rising edge of (CLKX + CLKY). When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a simple multipler with no accumulation SUB I This input is loaded into the control register on the rising edge of (CLKX + CLKY). This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted from the result and stored back in the output register. When SUB = 0 the contents of the output register are added to the result and stored back in the output register TC I This input is loaded into the control register on the rising edge of (CLKX + CLKY). When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y inputs are assumed to be in unsigned magnitude form RND I This input is loaded into the control register on the rising edge of (CLKX + CLKY). RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and XTP data |
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