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IDT72851L10PF Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72851L10PF Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 16 page  10 Commercial And Industrial Temperature Range IDT72801/728211/72821/72831/72841/72851 NOTE: 1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB) Figure 6. Read Cycle Timing tENH tENS NO OPERATION tOLZ VALID DATA tSKEW1 (1) tCLK tCLKH tCLKL tREF tREF tA tOE tOHZ RCLKA (RCLKB) RENA1, RENA2 ( RENB1, RENB2) EFA (EFB) QA0 - QA8 (QB0 - QB8) OEA (OEB) WCLKA (WCLKB) WENA1 (WENB1) WENA2 (WENB2) 3034 drw 07 tDS D0 (First Valid Write) tSKEW1 D0 D1 D3 D2 D1 tENS tFRL (1) tREF tA tOLZ tOE tA WCLKA (WCLKB) DA0 - DA8 (DB0 - DB8) WENA2 (WENB2) (If Applicable) RCLKA (RCLKB) EFA (EFB) RENA1, RENA2 ( RENB1, RENB2) QA0 - QA8 (QB0 - QB8) OEA (OEB) WENA1 (WENB1) 3034 drw 08 tENS tENS NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1V or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary ( EFA, EFB = LOW). Figure 7. First Data Word Latency Timing |
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