6.15

10

IDT7024S/L

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

W

W

W

W

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

CE

CE

CE

CE

CE, UB

UB

UB

UB

UB, LB

LB

LB

LB

2740 drw 10

ADDRESS

R/

W

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

(9)

R/

W

(2)

OE

ADDRESS

(6)

(4)

(4)

(7)

UB or LB

2740 drw 09

(9)

CE or SEM

(9)

(7)

(3)

NOTES:

1. R/

W or CE or UB & LB must be High during all address transitions.

UB or LB and a Low CE and a Low R/W for memory array writing cycle.

CE or R/W (or SEM or R/W) going High to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the

CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last,

CE, R/W, UB, or LB.

7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured +/- 500mV steady state with the Output Test

Load (Figure 2).

8. If

OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse

9. To access RAM,

met for either condition.