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IDT72413L45DB Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72413L45DB Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 11 page IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES 5.02 7 TIMING DIAGRAMS (Continued) 2748 drw 08 SHIFT OUT OUTPUT DATA OUTPUT READY A-DATA (1) (2) (3) (4) (5) (6) (7) B-DATA A or B NOTES: 1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied. 2. Shift Out goes HIGH causing the next step. 3. Output Ready goes LOW. 4. Read pointer is incremented. 5. Output Ready goes HIGH indicating that new data (B) will be available at the FIFO outputs after tORD ns. 6. If the FIFO has only one word loaded (A DATA) , Output Ready stays LOW and the A-DATA remains unchanged at the outputs. 7. Shift Out pulses applied when Output Ready is LOW will be ignored. Figure 6. The Mechanism of Shifting Data Out of the FIFO 2748 drw 06 SHIFT IN INPUT DATA INPUT READY STABLE DATA (1) (3) (4) (5) SHIFT OUT (2) tIPH t PT NOTES: 1. FIFO is initially full. 2. Shift Out pulse is applied. 3. Shift In is held HIGH. 4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH). Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH 2748 drw 07 SHIFT OUT OUTPUT DATA OUTPUT READY tSOH 1/fOUT t SOL 1/fOUT tRH tORL tODS A-DATA B-DATA (1) tODH C-DATA (2) tORD NOTES: 1. This data is loaded consecutively A, B, C. 2. Output data changes on the falling edge of SO after a valid Shift Out sequence, i.e., OR and SO are both high together. Figure 5. Output TIming |
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