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IDT72V71643 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT72V71643
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V71643 Datasheet(HTML) 6 Page - Integrated Device Technology

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COMMERCIAL TEMPERATURE RANGE
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
When the SFE bit in the Control Register is changed from low to high, the
evaluation starts. Two frames later, the complete frame evaluation (CFE) bit of
theframealignmentregister(FAR)changesfromlowtohightosignalthatavalid
offsetmeasurementisreadytobereadfrombits0to11oftheFARregister.The
SFE bit must be set to zero before a new measurement cycle is started.
In ST-BUS ® mode, the falling edge of the frame measurement signal (FE)
isevaluatedagainstthefallingedgeoftheST-BUS ® framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
See Table 6 and Figure 6 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
TheIDT72V71643providesuserswiththecapabilityofinitializingtheentire
ConnectionMemoryblockintwoframes.Tosetbits15to13ofeveryConnection
Memory location, first program the desired pattern in bits 9 to 7 of the Control
Register.
Setting the memory block program (MBP) bit of the control register high
enables the block programming mode. When the block programming enable
(BPE) bit of the Control Register is set to high, the block programming data will
beloadedintothebits15to13ofeveryConnectionMemorylocation.Theother
ConnectionMemorybits(bit12tobit0)areloadedwithzeros.Whenthememory
block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
Theloopbackcontrol(LPBK)bitofeachConnectionMemorylocationallows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TXn channel m routes to
the RXn channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delayoffsetregistersmustbesettozeroandthedevicemustbeinregularswitch
mode (DR3-0 = 0x0, 0x1 or 0x2).
DELAY THROUGH THE IDT72V71643
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
ties on a per-channel basis. For voice applications, Variable throughput delay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,Constantthroughputdelayisbestastheframeintegrityofthe
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the MOD1 and MOD0 bits of the Connection Memory.
VARIABLE DELAY MODE (MOD1-0 = 0x0)
In this mode, the delay is dependent only on the combination of source and
destination serial stream speed. Although the minimum delay achievable is
dependent on the input and output serial stream speed, if data is switched
out+3channelsoftheslowestdatarate,thedatawillbeswitchedoutinthesame
frame except if the input and output data rates are both 16 Mb/s (DR3-0 = 0x3).
(See Figure 2 for example).
For example, given the input data rate is 2 Mb/s and the output data rate is
8 Mb/s, input channel CH0 can be switch out by output channel CH12. In the
above example the input streams are slower than the output streams. Also, for
every2Mb/stimeslottherearefour8Mb/stimeslots,thusathree2Mb/schannel
delayequatesto12outputchanneltimeslots.SeeFigure2forthisexampleand
otherexamplesofminimumdelaytoguaranteetransmissioninthesameframe.
CONSTANT DELAY MODE (MOD1-0 = 0x1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple Data Memory buffer. Input channel data is written into
the Data Memory buffers during frame n will be read out during frame n+2.
Figure 1 shows examples of Constant Delay mode.
MICROPROCESSOR INTERFACE
The IDT72V71643’s microprocessor interface looks like a standard RAM
interface to improve integration into a system. With a 15-bit address bus and a
16-bit data bus, read and writes are mapped directly into Data and Connection
memories and require only one Master Clock cycle to access. By allowing the
internal memories to be randomly accessed in one cycle, the controlling
microprocessor has more time to manage other peripheral devices and can
more easily and quickly gather information and setup the switch paths.
Table 2 shows the mapping of the addresses into internal memory blocks,
Table 3 shows the Control Register information and Figure 13 and Figure 14
shows asynchronous and synchronous microprocessor accesses.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registersandmemoriesoftheIDT72V71643.Thetwomostsignificantbitsofthe
addressselectbetweentheregisters,DataMemory,andConnectionMemory.
IfA14andA13areHIGH,A12-A0areusedtoaddresstheDataMemory(Read
Only).IfA14isHIGHandA13isLOW,A12-A0areusedtoaddressConnection
Memory(Read/Write).IfA14isLOWandA13isHIGHA12-A9areusedtoselect
the Control Register, Frame Alignment Register, and Frame Offset Registers.
See Table 2 for mappings.
CONTROL REGISTER
As explained in the Serial Data Interface Timing and Switching Configura-
tions sections, after system power-up, the Control Register should be pro-
grammed immediately to establish the desired switching configuration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit (MBP), the Block Programming Data (BPD) bits, the Begin Block Program-
mingEnable(BPE),theOutputStandBy(OSB),StartFrameEvaluation(SFE),
and Data Rate Select bits (DR 3-0). As explained in the Memory Block
Programmingsection,theBPEbeginstheprogrammingiftheMBPbitisenabled.
This allows the entire Connection Memory block to be programmed with the
Block Programming Data bits.
CONNECTION MEMORY CONTROL
If the ODE pin or the OSB bit is high, the MOD1-0 bits of each Connection
Memory location controls the output drivers. See Table 1 for detail. The
Processor Channel (PC) mode is entered by a 1-0 of the MOD1-0 of the
ConnectionMemory.InProcessorChannelMode,thisallowsthemicroproces-
sor to access TX output channels. Once the MOD1-0 bits are set, the lower 8
bits of the Connection Memory will be output on the TX serial streams. Also
controlled in the Connection Memory is the Variable Delay mode or Constant
Delay mode. Each Connection Memory location allows the per-channel
selection between Variable and Constant throughput Delay modes and
Processor mode.


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