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IDT72V71643 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72V71643
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V71643 Datasheet(HTML) 5 Page - Integrated Device Technology

 
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COMMERCIAL TEMPERATURE RANGE
IDT72V71643 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
DESCRIPTION (CONTINUED)
The IDT72V71643 is capable of switching up to 4,096 x 4,096 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per channel basis.
The serial input streams (RX) and serial output streams (TX) of the
IDT72V71643 can be run up to 16.384 Mb/s allowing 256 channels per 125
µs
frame. Depending on the input and output data rates the device can support
up to 32 serial streams.
With two main operating modes, Processor mode and Connection Mode,
the IDT72V71643 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor (Connection Memory). As
controlandstatusinformationiscriticalindatatransmission,theProcessormode
isespeciallyusefulwhentherearemultipledevicessharingtheinputandoutput
streams.
Withthreemainconfigurationmodes,Regular,Mux/Demux,andSplitmode
the IDT72V71643 is designed to work in a mixed data-rate environment. In
Mux/Demux mode, all of the input streams work at one data rate and the output
streamsatanother. Dependingontheconfiguration,moreorlessserialstreams
will be available on the inputs or outputs to maintain a non-blocking switch. In
Split Mode, half of the input streams are set at one rate, while the other half are
settoanotherrate. Inthismode,bothinputandoutputstreamsaresymmetrical.
With data coming from multiple sources and through different paths, data
enteringthedeviceisoftendelayed.Tohandlethisproblem,theIDT72V71643
has a frame evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +4.5 clock cycles for speeds up
to 8 Mb/s or +2.5 clock cycles for 16 Mb/s. (See Table 8 for maximum allowable
skew).
The IDT72V71643 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in
debugging and ease use of the device without sacrificing capabilities.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F0i) is used to mark the 125
µs frame boundaries and to sequentially
address the input channels in Data Memory. The Data Memory is only written
by the device from the RX streams and can be read from either the TX streams
or the microprocessor.
DataoutputontheTXstreamsmaycomefromeithertheSerialInputStreams
(Data Memory) or from the microprocessor (Connection Memory). In the case
thatRXinputdataistobeoutput,theaddressesinConnectionMemoryareused
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particularstream.Inthatway,morethanonechannelcanoutputthesamedata.
InProcessormode,themicroprocessorwritesdatatotheConnectionMemory
locationscorrespondingtothestreamandchannelthatistobeoutput.Thelower
byte (8 least significant bits) of the Connection Memory is output every frame
untilthemicroprocessorchangesthedataormodeofthechannel.Byusingthis
Processor mode capability, the microprocessor can access input and output
time-slots on a per channel basis.
The most significant bits of the Connection Memory are used to control per
channelfunctionssuchasProcessormode,ConstantorVariableDelaymode,
three-state of output drivers, and the Loopback function.
OPERATING MODES
In addition to Regular mode where input and output streams are operating
atthesamerate,theIDT72V71643incorporatesaratematchingfunctionintwo
different modes: Split mode and Mux/Demux mode. In Split mode some of the
inputstreamsaresetatonerate,whileothersaresettoanotherrate. Bothinput
and output streams are symmetrical. In Mux/Demux mode, all input streams
areoperatingatthesamerate,whileoutputstreamsareoperatingatadifferent
rate. All configurations are non-blocking. These two modes can be entered
by setting the DR3-0 bits in the Control Register, see Table 5.
OUTPUT IMPEDANCE CONTROL
In order to put all streams in three-state, all per-channel three-state control
bits in the Connection Memory are set (MOD0 and MOD1 = 1) or both the ODE
pin and the OSB bit of the Control Register must be zero. If any combination
other than 0-0, for the ODE pin and the OSB bit, is used, the three-state control
ofthestreamswillbelefttothestateoftheMOD1andMOD0bitsoftheConnection
Memory. The IDT72V71643 incorporates a memory block programming
feature to facilitate three-state control after reset. See Table 1 for Output High-
Impedance Control.
SERIAL DATA INTERFACE TIMING
When a 16Mb/s serial data rate is required, the master clock frequency
will be running at 16.384MHz resulting in a single-bit per clock. For all other
cases, 2Mb/s, 4Mb/s, and 8Mb/s, the master clock frequency will be twice the
fastest data rate on the serial streams. Use Table 5 to determine clock speed
and DR3-0 bits in the Control Register to setup the device. The IDT72V71643
provides two different interface timing modes, ST-BUS® or GCI. The
IDT72V71643 automatically detects the presence of an input frame pulse and
identifies it as either ST-BUS® or GCI.
In ST-BUS®, when running at 16.384MHz, data is clocked out on the
falling edge and is clocked in on the subsquent rising-edge. At all other data
rates, there are two clock cycles per bit and every second falling edge of the
master clock marks a bit boundary and the data is clocked in on the rising edge
of CLK, three quarters of the way into the bit cell. See Figure 17 for timing.
In GCI format, when running at 16.384MHz, data is clocked out on the
rising edge and is clocked in on the subsquent falling edge. At all other data
rates, there are two clock cycles per bit and every second rising edge of the
master clock marks the bit boundary and data is clocked in on the falling edge
of CLK at three quarters of the way into the bit cell. See Figure 18 for timing.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.F0i).
Although input data is synchronous, delays can be caused by variable path
serialbackplanesandvariablepathlengths,whichmaybeimplementedinlarge
centralized and distributed switching systems. Because data is often delayed
this feature is useful in compensating for the skew between clocks.
Each input stream can have its own delay offset value by programming the
frameinputoffsetregisters(FOR,Table7).Theframeoffsetshownisafunction
ofthedatarate,andcanbeaslargeas+4.5masterclock(CLK)periodsforward
with a resolution of ½ clock period. To determine the maximum offset allowed
see Table 8.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V71643 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse F0i. Setting the start
frameevaluation(SFE)bitlowforatleastoneframestartsameasurementcycle.


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