6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

10

Timing Waveform of BUSY Arbritration Controlled

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).

NOTES:

BUSY input (71V421, slave) or output (71V321, master).

2.

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".

3026 drw 11

R/

(2)

(1)

(3)

,

(2)

ADDR

"A" AND "B"

ADDRESSES MATCH

3026 drw 12

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

3026 drw 13

(2)