IDT72605/IDT72615 CMOS SyncBiFIFO

256 x 18 x 2 and 512 x 18 x 2

COMMERCIAL TEMPERATURE RANGE

5.18

9

Table 2. Accessing Port A Resources Using

CS

Number of Words

in FIFO

From

To

EF

EF

PAE

PAE

PAF

PAF

FF

FF

0

0

LOW

LOW

HIGH

HIGH

1

n

HIGH

LOW

HIGH

HIGH

n+1

D-(m+1)

HIGH

HIGH

HIGH

HIGH

D-m

D-1

HIGH

HIGH

LOW

HIGH

D

D

HIGH

HIGH

LOW

LOW

NOTES:

n = Programmable Empty Offset (

m = Programmable Full Offset (

D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)

2704 tbl 12

Table 4. Internal Flag Truth Table.

17

16

15

14

13

12

11

10

98765

43210

X

X

XXXXXXX

A

→B FIFO Almost-Empty Flag Offset

17

16

15

14

13

12

11

10

98765

43210

X

X

XXXXXXX

A

→B FIFO Almost-Full Flag Offset

17

16

15

14

13

12

11

10

98765

43210

X

X

XXXXXXX

B

→A FIFO Almost-Empty Flag Offset

17

16

15

14

13

12

11

10

98765

43210

X

X

XXXXXXX

B

→A FIFO Almost-Full Flag Offset

NOTE:

1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.

2704 tbl 11

Table 3. Flag Offset Register Format.

PROGRAMMABLE FLAGS

The IDT SyncBiFIFO has eight flags: four flags for A

→BFIFO

(

(

fixed, while the Almost Empty and Almost Full offsets can be

set to any depth through the Flag Offset Registers (see Table

3). The flags are asserted at the depths shown in the Flag

Truth Table (Table 4). After reset, the programmable flag

offsets are set to 8. This means the Almost Empty flags are

asserted at Empty +8 words deep, and the Almost Full flags

are asserted at Full -8 words deep.

The

chronized to

between a rising

change state on the current clock; otherwise, the flag may not

change state until the next clock rising edge. For the specific

flag timings, refer to Figures 12-15.

PORT B CONTROL SIGNALS

The Port B control signal pins dictate the various operations

shown in Table 5. Port B is independent of

B. If R/

and on LOW-to-HIGH transition of

2704 tbl 10

CS

Read

Write

0000

B

→A FIFO A→B FIFO

0001

18-bit Bypass Path

0100

A

→B FIFO Almost-Empty

Flag Offset

0101

A

→B FIFO Almost-Full

Flag Offset

0110

B

→A FIFO Almost-Empty

Flag Offset

0111

B

→A FIFO Almost-Full

Flag Offset

1

X

X

X

Port A Disabled

PORT A CONTROL SIGNALS

The Port A control signals pins dictate the various opera-

tions shown in Table 2. Port A is accessed when

and is inactive if

when Data A can be written or read. If R/

data is written into input register on the LOW-to-HIGH transition

of

of bus and is read from output register into three-state buffer.

Refer to pin descriptions for more information.