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IDT72413L25SO Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72413L25SO Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 11 page IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES 5.02 3 DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Symbol Parameter Test Conditions Min. Max. Unit IIL Low-Level Input Current VCC = Max., GND ≤ VI ≤ VCC -10 — µA IIH High-Level Input Current VCC = Max., GND ≤ VI ≤ VCC —10 µA VOL Low-Level Output Current VCC = Min. IOL (Q0-4) Mil. 12mA — 0.4 V Com'l. 24mA IOL (IR, OR) (1) 8mA IOL (HF, AF/E) 8mA VOH High-Level Output Current VCC = Min. IOH (Q0-4) –4mA 2.4 — V IOH (IR, OR) –4mA IOH (HF, AF/E) –4mA IOS (2) Output Short-Circuit Current VCC = Max. VO = 0V -20 -110 mA IHZ Off-State Output Current VCC = Max. VO = 2.4V — 20 µA ILZ VCC = Max. VO = 0.4V -20 — ICC (3) Supply Current VCC = Max., OE=HIGH Mil. — 70 mA Inputs LOW, f=25MHz Com'l. — 60 NOTES: 2748 tbl 04 1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25mHz. 2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested. 3. For frequencies greater than 25MHz, ICC = 60mA + (1.5mA x [f - 25MHz]) commercial and ICC = 70mA + (1.5mA x [f - 25MHz]) military. OPERATING CONDITIONS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Commercial Military & Commercial Military & Commercial IDT72413L45 IDT72413L35 IDT72413L25 Symbol Parameters Figure Min. Max. Min. Max. Min. Max. Unit tSIH (1) Shift in HIGH Time 2 9 — 9 — 16 — ns tSIL (1) Shift in LOW TIme 2 11 — 17 — 20 — ns tIDS Input Data Set-up 2 0 — 0 — 0 — ns tIDH Input Data Hold Time 2 13 — 15 — 25 — ns tSOH (1) Shift Out HIGH Time 5 9 — 9 — 16 — ns tSOL Shift Out LOW Time 5 11 — 17 — 20 — ns tMRW Master Reset Pulse 8 20 — 30 — 35 — ns tMRS Master Reset Pulse to SI 8 20 — 35 — 35 — ns NOTE: 2748 tbl 05 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1 µF directly between VCC and GND with very short lead length is recommended. |
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