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IDT72805LB Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT72805LB
Description  CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72805LB Datasheet(HTML) 1 Page - Integrated Device Technology

 
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FEBRUARY 2003
CMOS DUAL SyncFIFO™
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1,024 x 18, DUAL 2,048 x 18
and DUAL 4,096 x 18
IDT72805LB
IDT72815LB
IDT72825LB
IDT72835LB
IDT72845LB
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT and the IDT logo are registered trademarks. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3139/4
FEATURES:
••••• The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs
••••• The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs
••••• The IDT72825LB is equivalent to two IDT72225LB 1,024 x 18 FIFOs
••••• The IDT72835LB is equivalent to two IDT72235LB 2,048 x 18 FIFOs
••••• The IDT72845LB is equivalent to two IDT72245LB 4,096 x 18 FIFOs
••••• Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint
••••• Ideal for the following applications:
-
Network switching
-
Two level prioritization of parallel data
-
Bidirectional data transfer
-
Bus-matching between 18-bit and 36-bit data paths
-
Width expansion to 36-bit per package
-
Depth expansion to 8,192 words per package
••••• 10ns read/write cycle time, 6.5ns access time
••••• IDT Standard or First Word Fall Through timing
FUNCTIONAL BLOCK DIAGRAM
••••• Single or double register-buffered Empty and Full Flags
••••• Easily expandable in depth and width
••••• Asynchronous or coincident Read and Write clocks
••••• Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
••••• Half-Full flag capability
••••• Output Enable puts output data bus in high-impedance state
••••• High-performance submicron CMOS technology
••••• Available in the 128-pin Thin Quad Flatpack (TQFP). Also
available for the IDT72805LB/72815LB/72825LB, in the 121-lead,
16 x 16 mm plastic Ball Grid Array (PBGA)
••••• Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
DESCRIPTION:
The IDT72805LB/72815LB/72825LB/72835LB/72845LB are dual 18-bit-wide
synchronous(clocked)First-in,First-out(FIFO)memories.OnedualIDT72805LB/
72815LB/72825LB/72835LB/72845LB device is functionally equivalent to two
INPUT
REGISTER
OUTPUT
REGISTER
OFFSET
REGISTER
FLAG
LOGIC
FFA/IRA
PAFA
EFA/
ORA
PAEA
HFA/(WXOA)
READ
POINTER
READ
CONTROL
LOGIC
WRITE
CONTROL
LOGIC
WRITE
POINTER
EXPANSION
LOGIC
RESET
LOGIC
WENA
DA0-DA17
LDA
RSA
(
HFA)/WXOA
WXIA
RENA
RCLKA
OEA QA0-QA17
RXOA
RXIA
FLA
WCLKA
INPUT
REGISTER
OUTPUT
REGISTER
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
OFFSET
REGISTER
FLAG
LOGIC
FFB/IRB
PAFB
EFB/ORB
PAEB
HFB/(WXOB)
READ
POINTER
READ
CONTROL
LOGIC
WRITE
CONTROL
LOGIC
WRITE
POINTER
EXPANSION
LOGIC
RESET
LOGIC
WENB
DB0-DB17
LDB
RSB
(
HFB)/WXOB
WXIB
RENB
RCLKB
OEB
QB0-QB17
RXOB
RXIB
FLB
WCLKB
3139 drw 01
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18


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