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IDT72805LB Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT72805LB
Description  CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72805LB Datasheet(HTML) 6 Page - Integrated Device Technology

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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
6
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0
°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C + 85°C)
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 1
AC TEST CONDITIONS
Figure 1. Output Load
* Includes jig and scope capacitances.
Commercial
Com’l & Ind’l(1)
Commercial
IDT72805LB10
IDT72805LB15
IDT72805LB25
IDT72815LB10
IDT72815LB15
IDT72815LB25
IDT72825LB10
IDT72825LB15
IDT72825LB25
IDT72835LB10
IDT72835LB15
IDT72835LB25
IDT72845LB10
IDT72845LB15
IDT72845LB25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
100
66.7
40
MHz
tA
Data Access Time
2
6.5
2
10
3
15
ns
tCLK
Clock Cycle Time
10
15
25
ns
tCLKH
Clock HIGH Time
4.5
6
10
ns
tCLKL
Clock LOW Time
4.5
6
10
ns
tDS
Data Setup Time
3
4
6
ns
tDH
Data Hold Time
0
1
1
ns
tENS
Enable Setup Time
3
4
6
ns
tENH
Enable Hold Time
0
1
1
ns
tRS
Reset Pulse Width(2)
10
15
25
ns
tRSS
Reset Setup Time
8
10
15
ns
tRSR
Reset Recovery Time
8
10
15
ns
tRSF
Reset to Flag and Output Time
15
15
25
ns
tOLZ
Output Enable to Output in Low-Z(3)
0—
0—
0
ns
tOE
Output Enable to Output Valid
6
8
12
ns
tOHZ
Output Enable to Output in High-Z(3)
16
18
1
12
ns
tWFF
Write Clock to Full Flag
6.5
10
15
ns
tREF
Read Clock to Empty Flag
6.5
10
15
ns
tPAFA
Clock to Asynchronous Programmable
17
20
35
ns
Almost-Full Flag
tPAFS
Write Clock to Synchronous
8
10
12
ns
Programmable Almost-Full Flag
tPAEA
Clock to Asynchronous Programmable
17
20
35
ns
Almost-Empty Flag
tPAES
Read Clock to Synchronous
8
10
12
ns
Programmable Almost-Empty Flag
tHF
Clock to Half-Full flag
17
20
35
ns
tXO
Clock to Expansion Out
6.5
10
15
ns
tXI
Expansion In Pulse Width
3
6.5
10
ns
tXIS
Expansion In Setup Time
3
5
10
ns
tSKEW1
Skew time between Read Clock &
5
6
10
ns
Write Clock for
FF/IR and EF/OR
tSKEW2(4)
Skew time between Read Clock &
12
15
17
ns
Write Clock for
PAE and PAF
3139 drw 03
30pF*
1.1K
5V
D.U.T.
680
NOTES:
1. Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. tSKEW2 applies to synchronous
PAE and synchronous PAF only.


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