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IDT723651L20PF Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT723651L20PF Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 23 page 4 IDT723631/723641/723651 CMOS SyncFIFO ™ 512 x 36, 1024 x 36, 2048 x 36 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Symbol Name I/O Description A0-A35 Port-A Data I/O 36-bit bidirectional data port for side A. AE Almost-Empty Flag O Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to the value in the almost-empty register (X). AF Almost-Full Flag. O Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in the FIFO is less than or equal to the value in the almost-full offset register (Y). B0-B35 Port-B Data. I/O 36-bit bidirectional data port for side B. CLKA Port-A Clock I CLKA is a continuous clock that synchronizes all data transfers through port-A and may be aynchronous or coincident to CLKB. IR and AF are synchronous to the LOW-to-HIGH transition of CLKA. CLKB Port-B Clock I CLKB is a continuous clock that synchronizes all data transfers through port-B and may be asynchronous or coincident to CLKA. OR and AE are synchro nous to the LOW-to-HIGH transition of CLKB. CSA Port-A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB Port-B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. ENA Port-A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. ENB Port-B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. FS1/ SEN, Flag-Offset Select 1/ I FS1/ SEN and FS0/SD are dual-purpose inputs used for flag offset register FS0/SD Serial Enable, programming. During a device reset, FS1/ SEN and FS0/SD selects the flag Flag Offset 0/ offset programming method. Three offset register programming methods are Serial Data available: automatically load one of two preset values, parallel load from port A, and serial load. When serial load is selected for flag offset register program- ming, FS1/ SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/ SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 18/20/22. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. IR Input-Ready Flag O IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit data and prevents further writes. IR is set LOW during reset and is set HIGH after reset. MBA Port-A Mailbox Select I A HIGH level chooses a mailbox register for a port-A read or write operation. MBB Port-B Mailbox Select I A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO data for output. MBF1 Mail1 Register Flag O MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH by a reset. 3023 tbl 01 |
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