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IDT72510L25J Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72510L25J Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 32 page 5.31 3 IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTIONS Symbol Name I/O Description DA0-DA15 Data A I/O Data inputs and outputs for 16 bits of the 18-bit Port A bus. DA16-DA17 Parity A I/O DA16 is the parity bit for DA0-DA7. DA17 is the parity bit for DA8- DA15. DA16 and DA17 can be used as two extra data bits if the parity generate function is disabled. CSA Chip Select A I Port A is accessed when Chip Select A is LOW. DSA Data Strobe A I Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the falling edge of Data Strobe when Chip Select is LOW. R/ WA Read/Write A I This pin controls the read or write direction of Port A. When CSA is LOW and R/ WA is HIGH, data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data is written into Port A on the rising edge of DSA. A0, A1 Addresses I When Chip Select A is asserted, A0, A1, and Read/Write A are used to select one of six internal resources. DB0-DB7 Data B I / O Data inputs and outputs for 8 bits of the 9-bit Port B bus. DB8 Parity B I / O DB8 is the parity bit for DB0-DB7. DB8 can be used as a data bit if the parity generate function is disabled. RB (DSB) Read B I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface ( RB) or as part of a Motorola-style interface (DSB). As an Intel-style interface, data is read from Port B on a falling edge of RB. As a Motorola-style interface, data is read on the falling edge of DSB or written on the rising edge of DSB through Port B. The Default is Intel- style processor mode ( RB as an input). WB (R/WB) Write B I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface ( WB) or as part of a Motorola-style interface (R/WB). As an Intel style interface, data is written to Port B on a rising edge of WB. As a Motorola-style interface, data is read (R/ WB = HIGH) or written (R/ WB = LOW) to Port B in conjunction with a Data Strobe B falling or rising edge. The Default is Intel-style processor mode ( WB as input). RER Reread I Loads A-to-B FIFO Read Pointer with the value of the Reread Pointer when LOW. REW Rewrite I Loads B-to-A FIFO Write Pointer with the value of the Rewrite Pointer when LOW. LDRER Load Reread I Loads the Reread Pointer with the value of the A-to-B FIFO Read Pointer when HIGH. This signal is accessible through the Command Register. LDREW Load Rewrite I Loads the Rewrite Pointer with the value of the B-to-A FIFO Write Pointer when HIGH. This signal is accessible through the Command Register. REQ Request I When Port B is programmed in peripheral mode, asserting this pin begins a data transfer. Request can be programmed either active HIGH or active LOW. 2669 tbl 01 |
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