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IDT72421 Datasheet(PDF) 10 Page - Integrated Device Technology

Part # IDT72421
Description  CMOS SyncFIFOO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72421 Datasheet(HTML) 10 Page - Integrated Device Technology

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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
10
Figure 8. Full Flag Timing
Figure 9. Empty Flag Timing
NOTE:
1.
When tSKEW1
≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1
< minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK+ tSKEW1
The Latency Timings apply only at the Empty Boundary (
EF = LOW).
NOTE:
1. Only one of the two write enable inputs,
WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
tSKEW1
tDS
tSKEW1
tENH
tENH
NEXT DATA READ
DATA READ
WCLK
D0 - D8
FF
WEN1
WEN2
(If Applicable)
RCLK
REN1,
REN2
Q0 - Q8
tWFF
tWFF
tWFF
tENS
tENS
DATA IN OUTPUT REGISTER
OE LOW
NO WRITE
NO WRITE
2655 drw 10
tA
tA
tENS
tENS
tENS
(1)
tENS
(1)
tENH
tENH
NO WRITE
tA
tDS
tDS
DATA WRITE 1
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tENH
DATA WRITE 2
WCLK
D0 - D8
RCLK
EF
REN1,
REN2
OE
Q0 - Q8
DATA READ
tSKEW1
(1)
tFRL
tFFL
DATA IN OUTPUT REGISTER
(1)
tSKEW1
LOW
WEN2
(If Applicable)
tREF
tREF
tREF
WEN1
2655 drw 11


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