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IDT72421 Datasheet(PDF) 6 Page - Integrated Device Technology

Part # IDT72421
Description  CMOS SyncFIFOO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72421 Datasheet(HTML) 6 Page - Integrated Device Technology

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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
6
Figure 3. Offset Register Location and Default Values
86
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
IDT72421 - 64 x 9-BIT
IDT72201 - 256 x 9-BIT
IDT72211 - 512 x 9-BIT
7
7
80
(MSB)
1
80
0
0
80
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Empty Offset (LSB)
Default Value 007H
IDT72221 - 1,024 x 9-BIT
IDT72231 - 2,048 x 9-BIT
IDT72241 - 4,096 x 9-BIT
7
80
80
(MSB)
0000
2
(MSB)
000
3
80
(MSB)
00
1
80
(MSB)
00
1
5
65
80
8
0
8
(MSB)
1
0
IDT72251 8,192 x 9-BIT
80
Empty Offset (LSB)
Default Value 007H
7
80
(MSB)
00000
4
87
0
Full Offset (LSB) Reg.
Default Value 007H
80
2
(MSB)
000
80
Full Offset (LSB)
Default Value 007H
7
80
(MSB)
0000
3
80
Full Offset (LSB)
Default Value 007H
7
80
(MSB)
00000
4
2655 drw 05
Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe
WriteEnable2/Load(WEN2/
LD)pinissetLOWandbothReadEnables(REN1,
REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of the
Read Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.


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