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IDT6168SA15SOB Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT6168SA15SOB Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 9 page 4 IDT6168SA/LA CMOS Static RAM 16K (4K x 4-Bit) Military, Industrial, and Co mmercial Temperature Ranges Low VCC Data Retention Waveform AC Test Conditions Figure 1. AC Test Load Figure 2. AC Test Load (for tCHZ, tCLZ, tWHZ and tOW) *Includes scope and jig capacitances Data Retention Characteristics (LA Version Only) VLC = 0.2V, VHC = VCC 0.2V 3090 drw 03 VCC CS DATA RETENTION MODE 4.5V 4.5V VDR ≥ 2V VIH VIH tR tCDR VDR , 3090 drw 04 480 Ω 30pF* 255 Ω DATAOUT 5V 3090 drw 05 480 Ω 5pF* 255 Ω DATAOUT 5V Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2 3090 tbl 11 NOTES: 1. TA = +25°C. 2. at VCC = 2V 3. at VCC = 3V 4. tRC = Read Cycle Time. 5. This parameter is guaranteed by device characterization, but is not production tested. IDT6168LA Symbol Parameter Test Condition Min. Typ. (1) Max. Unit VDR VCC for Data Retention 2.0 ____ ____ V ICCDR Data Retention Current CS > VHC VIN > VHC or < VLC MIL. ____ ____ 0.5 (2) 1.0(3) 100 (2) 150(3) µA COM'L. ____ ____ 0.5 (2) 1.0(3) 20 (2) 30(3) µA tCDR (5) Chip Deselect to Data Retention Time 0 ____ ____ ns tR (5) Operation Recovery Time tRC (4) ____ ____ ns 3090 tbl 10 |
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