Electronic Components Datasheet Search |
|
IDT72402 Datasheet(PDF) 8 Page - Integrated Device Technology |
|
IDT72402 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 9 page 5.01 8 IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES 2747 drw 16 D0 D1 D2 D3 IR SI Q0 Q1 Q2 Q3 SO OR MR D0 D1 D2 D3 Q0 Q1 Q2 Q3 MR D0 D1 D2 D3 Q0 Q1 Q2 Q3 MR D0 D1 D2 D3 Q0 Q1 Q2 Q3 MR D0 D1 D2 D3 Q0 Q1 Q2 Q3 MR D0 D1 D2 D3 Q0 Q1 Q2 Q3 MR D0 D1 D2 D3 SI IR Q0 Q1 Q2 Q3 OR SO MR D0 D1 D2 D3 SI IR Q0 Q1 Q2 Q3 OR SO MR D0 D1 D2 D3 SI IR Q0 Q1 Q2 Q3 OR SO MR SHIFT OUT COMPOSITE OUTPUT READY MR SHIFT IN COMPOSITE INPUT READY IR SI SO OR IR SI SO OR IR SI SO OR IR SI SO OR IR SI SO OR NOTES: 1. When the memory is empty, the last word will remain on the outputs until the Master Reset is strobed or a new data word falls through to the output. However, OR will remain LOW, indicating data at the output is not valid. 2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs. 3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought LOW. 4. When the Master Reset is brought Low, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the Master Reset goes HIGH, the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the Master Reset is ended, IR will go HIGH, but the data in the inputs will not enter the memory until SI goes HIGH. 5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and Output Ready flags. This is due to the variation of delays of the FIFOs. Figure 11. 192 x 12 Depth and Width Expansion APPLICATIONS 2747 drw 15 D0 D1 D2 D3 IR SI Q0 Q1 Q2 Q3 SO OR MR D0 D1 D2 D3 IR SI Q0 Q1 Q2 Q3 SO OR MR SHIFT IN INPUT READY DATA IN MR OUTPUT READY SHIFT OUT DATA OUT NOTE: 1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. Figure 10. 128 x 4 Depth Expansion |
Similar Part No. - IDT72402 |
|
Similar Description - IDT72402 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |