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IDT7015 Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7015 Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 20 page IDT7015S/L HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.12 7 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) IDT7015X12 IDT7015X15 IDT7015X17 Com'l. Only Com'l. Only Com'l. Only Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 — 15 — 17 — ns tAA Address Access Time — 12 — 15 — 17 ns tACE Chip Enable Access Time (3) — 12 — 15 — 17 ns tAOE Output Enable Access Time — 8 — 10 — 10 ns tOH Output Hold from Address Change 3 — 3 — 3 — ns tLZ Output Low-Z Time (1, 2) 3 — 3 — 3 — ns tHZ Output High-Z Time (1, 2) — 10 — 10 — 10 ns tPU Chip Enable to Power Up Time (2) 0 — 0 — 0 — ns tPD Chip Disable to Power Down Time (2) — 12 — 15 — 17 ns tSOP Semaphore Flag Update Pulse ( OE or SEM) 10 — 10 — 10 — ns tSAA Semaphore Address Access Time — 12 — 15 — 17 ns IDT7015X20 IDT7015X25 IDT7015X35 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 — 25 — 35 — ns tAA Address Access Time — 20 — 25 — 35 ns tACE Chip Enable Access Time (3) —20—25 —35 ns tAOE Output Enable Access Time — 12 — 13 — 20 ns tOH Output Hold from Address Change 3 — 3 — 3 — ns tLZ Output Low-Z Time (1, 2) 3— 3— 3— ns tHZ Output High-Z Time (1, 2) —12—15 —20 ns tPU Chip Enable to Power Up Time (2) 0— 0— 0— ns tPD Chip Disable to Power Down Time (2) —20—25 —35 ns tSOP Semaphore Flag Update Pulse ( OE or SEM) 10—10 —15— ns tSAA Semaphore Address Access Time — 20 — 25 — 35 ns NOTES: 2954 tbl 11 1. Transition is measured ±200mV from Low- or High-impedance voltage with the Output test load (Figure 2). 2. This parameter is guaranteed by device characterization but not tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. "X" in part numbers indicates power rating (S or L). |
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