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IDT72103L35J Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72103L35J Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 31 page 5.37 2 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES DESCRIPTION (CONTINUED) The IDT72103/72104 may be configured to handle serial word widths of four or greater using IDT’s unique Flexishift feature. Flexishift allows serial width and depth expansion without external components. For example, you may config- ure a 4K x 24 FIFO using three IDT72104s in a serial width expansion configuration. Seven flags are provided to signal memory status of the FIFO. The flags are FF (Full), AF (7/8 full), FF–1 (Full-minus- one), EF (Empty), AE (1/8 full), EF+1 (Empty-plus-one), and HF (Half-full). Read ( R) and Write (W) control pins are provided for asynchronous and simultaneous operations. An output en- able ( OE) control pin is available on the parallel output port for high-impedance control. The depth expansion control pins XO and Xl are provided to allow cascading for deeper FlFOs. The IDT72103/72104 are manufactured using IDT’s CMOS technology. PIN CONFIGURATIONS PLCC TOP VIEW 7 8 9 10 11 12 13 J44-1 39 38 37 36 35 34 33 43 2 1 43 INDEX 5 644 42 41 40 14 15 16 17 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 D 0 XI SO/PO SOX SOCP Q 0 SO AEF FF-1 FF GND FL/RT RS SI SICP SIX GND XO/HF EF EF+1 OE SI/PI 2753 drw 03 |
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