6.4

5

IDT7198S/L

CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls

MILITARY TEMPERATURE RANGE

NOTES:

1.

WE is HIGH for Read cycle.

2. Device is continuously selected,

3. Address valid prior to or coincident with

4.

OE is LOW.

5. Transition is measured

±200mV from steady state voltage.

TIMING WAVEFORM OF READ CYCLE NO. 1

(1)

ADDRESS

OE

2985 drw 07

(5)

(5)

(5)

(5)

DATA VALID

± 10%, Military Temperature Range)

7198S20

7198S25

7198S35/45

7198S55

7198S70

7198S85

7198L20

7198L25

7198L35/45

7198L55

7198L70

7198L85

Symbol

Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Read Cycle

Read Cycle Time

20

—

25

—

35/45

—

55

—

70

—

85

—

ns

Address Access Time

—

19

—

25

—

35/45

—

55

—

70

—

85

ns

—

20

—

25

—

35/45

—

55

—

70

—

85

ns

5

—

5

—

5

—

5

—

5

—

5

—

ns

Output Enable to Output Valid

—

9

—

11

—

20/25

—

35

—

45

—

55

ns

(2)

Output Enable to Output in Low-Z

5

—

5

—

5

—

5

—

5

—

5

—

ns

—

8

—

10

—

14

—

20

—

25

—

30

ns

(2)

Output Disable to Output in High-Z

—

8

—

9

—

15

—

20

—

25

—

30

ns

Output Hold from Address Change

5

—

5

—

5

—

5

—

5

—

5

—

ns

(2)

Chip Select to Power Up Time

0

—

0

—

0

—

0

—

0

—

0

—

ns

(2)

Chip Deselect to Power Down Time

—

20

—

25

—

35/45

—

55

—

70

—

85

ns

NOTES:

2985 tbl 11

1. Both chip selects must be active low for the device to be selected.

2. This parameter is guaranteed by device characterization but is not production tested.