6.4

6

IDT7198S/L

CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls

MILITARY TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 2

(1, 2, 4)

ADDRESS

2985 drw 08

DATA VALID

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO. 3

(1, 3, 4)

CURRENT

2985 drw 09

(5)

(5)

DATA VALID

NOTES:

1.

WE is HIGH for Read cycle.

2. Device is continuously selected,

3. Address valid prior to or coincident with

4.

OE is LOW.

5. Transition is measured

±200mV from steady state voltage.

± 10%, All Temperature Ranges)

7198S20

7198S25

7198S35/45

7198S55

7198S70

7198S85

7198L20

7198L25

7198L35/45

7198L55

7198L70

7198L85

Symbol

Parameter

Min. Max. Min. Max. Min.

Max. Min. Max. Min. Max. Min. Max. Unit

Write Cycle

Write Cycle Time

17

—

20

—

30/40

—

50

—

60

—

75

—

ns

17

—

20

—

25/35

—

50

—

60

—

75

—

ns

Address Valid to End-of-Write

17

—

20

—

25/35

—

50

—

60

—

75

—

ns

Address Set-up Time

0

—

0

—

0

—

0

—

0

—

0

—

ns

Write Pulse Width

17

—

20

—

25/35

—

50

—

60

—

75

—

ns

Write Recovery Time

0

—

0

—

0

—

0

—

0

—

0

—

ns

(2)

Write Enable to Output in High-Z

—

5/6

—

7

—

10/15

—

25

—

30

—

40

ns

Data Valid to End-of-Write

10

—

13

—

15/20

—

25

—

30

—

35

—

ns

Data Hold Time

0

—

0

—

0

—

0

—

0

—

0

—

ns

(2)

Output Active from End-of-Write

5

—

5

—

5

—

5

—

5

—

5

—

ns

NOTES:

2985 tbl 12

1. Both chip selects must be active low for the device to be selected.

2. This parameter is guaranteed by device characterization but is not production tested.