6.2

7

IDT7187S/L

CMOS STATIC RAM 64K (64K x 1-BIT)

MILITARY TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WE

WE CONTROLLED TIMING)

(1,2,3,4)

NOTES:

1.

WE or CS must be HIGH during all address transitions.

CS and a LOW WE.

CS or WE going HIGH to the end of the write cycle.

4. If the

CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.

5. Transition is measured

±200mV from steady state with a 5pF load (including scope and jig).

NOTES:

1.

WE or CS must be HIGH during all address transitions.

CS and a LOW WE.

CS or WE going HIGH to the end of the write cycle.

4. If the

CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.

5. Transition is measured

±200mV from steady state with a 5pF load (including scope and jig).

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CS

CS CONTROLLED TIMING)

(1,2,4)

CS

2986 drw 09

ADDRESS

WE

(5)

VALID DATA

(5)

CS

2986 drw 10

ADDRESS

WE

AS

t

t

VALID DATA

(3)