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IDT7143LA25J Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7143LA25J Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 16 page 6.42 IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges 7 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3) NOTES: 1. Transition is measured 0mV fromLow or High-impedance voltage with load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part number indicates power rating (SA or LA). 7133X20 7143X20 Com'l Only 7133X25 7143X25 Com'l, Ind & Military 7133X35 7143X35 Com'l, Ind & Military Unit Symbol Parameter Min.Max. Min.Max.Min.Max. READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 12 ____ 15 ____ 20 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0 ____ ns tLZ Output Low-Z Time (1,2) 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time (1,2) ____ 12 ____ 15 ____ 20 ns tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 20 ____ 50 ____ 50 ns 2746 tbl 10a 7133X45 7143X45 Com'l & Military 7133X55 7143X55 Com'l, Ind & Military 7133X70/90 7143X70/90 Com'l & Military Unit Symbol Parameter Min.Max. Min.Max.Min.Max. READ CYCLE tRC Read Cycle Time 45 ____ 55 ____ 70/90 ____ ns tAA Address Access Time ____ 45 ____ 55 ____ 70/90 ns tACE Chip Enable Access Time ____ 45 ____ 55 ____ 70/90 ns tAOE Output Enable Access Time ____ 25 ____ 30 ____ 40/40 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0/0 ____ ns tLZ Output Low-Z Time (1,2) 0 ____ 5 ____ 5/5 ____ ns tHZ Output High-Z Time (1,2) ____ 20 ____ 20 ____ 25/25 ns tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ 0/0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 50 ____ 50 ____ 50/50 ns 2746 tbl 10b |
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