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IDT7198L Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7198L Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 8 page 6.4 7 IDT7198S/L CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 ( WE WE CONTROLLED TIMING) (1, 2, 3, 7) TIMING WAVEFORM OF WRITE CYCLE NO. 2 ( CS CS CONTROLLED TIMING) (1) NOTES: 1. WE, CS1 or CS2 must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW WE, a LOW CS1 and a LOW CS2. 3. tWR is measured from the earlier of CS1, CS2 or WE going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, outputs remain in the high-impedance state. 6. Transition is measured ±200mV from steady state. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. CS1, 2 DATAIN ADDRESS WE DATAOUT OE 2985 drw 10 tAW tWR tDW tWC tWP tDH tWHZ tOW tAS (6) (6) (4) (4) (7) DATA VALID CS1, 2 DATAIN ADDRESS WE ttWR 2985 drw 11 tAW tDW tWC tCW tDH tAS DATA VALID |
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