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IDT49C460AFFB Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT49C460AFFB Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 32 page  FEATURES: • Fast Detect Correct — IDT49C460E 10ns (max.) 14ns (max.) — IDT49C460D 12ns (max.) 18ns (max.) — IDT49C460C 16ns (max.) 24ns (max.) — IDT49C460B 25ns (max.) 30ns (max.) — IDT49C460A 30ns (max.) 36ns (max.) — IDT49C460 40ns (max.) 49ns (max.) • Low-power CMOS — Commercial: 95mA (max.) — Military: 125mA (max.) • Improves system memory reliability — Corrects all single bit errors, detects all double and some triple-bit errors • Cascadable — Data words up to 64-bits • Built-in diagnostics — Capable of verifying proper EDC operation via software control • Simplified byte operations — Fast byte writes possible with separate byte enables • Functional replacement for 32- and 64-bit configurations of the AM29C60 and AM29C660 • Available in PGA, PLCC and Fine Pitch Flatpack • Military product compliant to MIL-STD-883, Class B • Standard Military Drawing #5962–88533 Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995 ©1995 Integrated Device Technology, Inc. 11.6 DSC-9017/8 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT The IDT logo is a registered trademark of Integrated Device Technology, Inc. DESCRIPTION: The IDT49C460s are high-speed, low-power, 32-bit Error Detection and Correction Units which generate check bits on a 32-bit data field according to a modified Hamming Code and correct the data word when check bits are supplied. The IDT49C460s are performance-enhanced functional replace- ments for 32-bit versions of the 2960. When performing a read operation from memory, the IDT49C460s will correct 100% of all single bit errors and will detect all double bit errors and some triple bit errors. The IDT49C460s are easily cascadable to 64-bits. Thirty- two-bit systems use 7 check bits and 64-bit systems use 8 check bits. For both configurations, the error syndrome is made available. The IDT49C460s incorporate two built-in diagnostic modes. Both simplify testing by allowing for diagnostic data to be entered into the device and to execute system diagnostics functions. They are fabricated using a CMOS technology designed for high-performance and high-reliability. The devices are pack- aged in a 68-pin ceramic PGA, PLCC and Ceramic Quad Flatpack. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. 1 FUNCTIONAL BLOCK DIAGRAM DATA LATCH ERROR CORRECT ERROR DECODE MUX DATA LATCH CHECK BIT GENERATE MUX MUX CHECK BIT IN LATCH DIAGNOSTIC LATCH SYNDROME GENERATE ERROR DETECT CONTROL LOGIC MUX 8 8 8 5 8 8 8 32 32 4 32 13 CB0–7 DATA0–31 OE BYTE0–3 LEIN LEDIAG LEOUT/ GENERATE CORRECT CODE ID1,0 DIAG MODE1,0 SC0–7 OESC ERROR MULT ERROR 2584 drw 01 IDT49C460 IDT49C460A IDT49C460B IDT49C460C IDT49C460D IDT49C460E |
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