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IDT49C460AFFB Datasheet(PDF) 8 Page - Integrated Device Technology

Part No. IDT49C460AFFB
Description  32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT49C460AFFB Datasheet(HTML) 8 Page - Integrated Device Technology

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IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING MODE SELECTION
Tables 2 and 3 describe the nine operating modes of the
IDT49C460s. The Diagnostic Mode pins — DIAG MODE0,1
— define four basic areas of operation.
GENERATE and
CORRECT further divide operation into 8 functions, with
CODE ID1,0 defining the ninth mode as the Internal Mode.
Generate Mode is used to display the check bits on the
outputs SC0–7.
The Diagnostic Generate Mode displays
check bits as stored in the Diagnostic Latch.
Detect Mode provides an indication of errors or multiple
errors on the outputs
ERROR and MULT ERROR. Single bit
errors are not corrected in this mode. The syndrome bits are
provided on the outputs SC0–7. For the Diagnostic Detect
Mode, the syndrome bits are generated by comparing the
internally generated check bits from the Data In Latch with
check bits stored in the diagnostic latch rather than with the
check bit latch contents.
Correct Mode is similar to the Detect Mode except that
single bit errors will be complemented (corrected) and made
available as input to the Data Out Latches.
Again, the
Diagnostic Correct Mode will correct single bit errors as
determined by syndrome bits generated from the data input
and contents of the diagnostic latches.
The Initialize Mode provides check bits for all zero bit data.
Data Input Latches are set, latched to a logic zero and made
available as input to the Data Out Latches.
The Internal Mode disables the external control pins DIAG
MODE0,1 and CORRECT to be defined by the Diagnostic
Latch. Even CODE ID1,0, although externally set to the 01
code, can be redefined from the Diagnostic Latch data.
Code ID1
Code ID0
Slice Selected
0
0
32-Bit
0
1
Internal Control Mode
1
0
64-Bit, Lower 32–Bit (0–31)
1
1
64-Bit, Upper 32-Bit (32–63)
2584 tbl 04
Table 4. Slice Identification
DATA0–31
DATA0–31
CB7
HIGH
CB6
C6
CB5
C5
CB4
C4
CB3
C3
CB2
C2
CB1
C1
CB0
C0
SC7
NC
SC6
S6/C6
SC5
S5/C5
SC4
S4/C4
SC3
S3/C3
SC2
S2/C2
SC1
S1/C1
SC0
S0/C0
CODE ID1,0
IDT49C460
0,0
2584 drw 05
Figure 1. 32-Bit Configuration
Figure 2. 64-Bit Configuration
BYTE3
BYTE2
BYTE1
BYTE0
C0
C1
C2
C3
C4
C5
C6
DATA
CHECK BITS
0
7
8
15
16
23
24
31
2584 drw 07
BYTE7
BYTE6
BYTE5
BYTE4
BYTE3
BYTE2
BYTE1
BYTE0
C0
C1
C2
C3
C4
C5
C6
C7
DATA
CHECK BITS
0
7
8
15
16
23
24
31
32
39
40
47
48
55
56
63
2584 drw 08
Figure 3. 32-Bit Data Format
Figure 4. 64-Bit Data Format
DATA0–31
DATA32–63
DATA INPUT
CHECK–BIT INPUTS
1/8
IDT74FCT240
DATA
CB0–7
OESC
CODE ID1,0
SC0–7
IDT49C460
(LOWER 32 BITS)
DATA
CB0–7
OESC
CODE ID1,0
SC0–7
IDT49C460
(UPPER 32 BITS)
ERROR
MULT
ERROR
MULT
ERROR
ERROR
SYNDROME/
CHECK BITS
1,1
1,0
OESC
32
32
8
8
8
2584 drw 06


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