11.6

5

IDT49C460/A/B/C/D/E

32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS

Pin Name

I/O

Description

I/O

32 bidirectional data lines provide input to the Data Input Latch and Diagnostic Latch and also receive output from

I

Eight check bit input lines input check bits for error detection and also used to input syndrome bits for error

correction in 64-bit applications.

I

Latch Enable is for the Data Input Latch. Controls latching of the input data. Data Input Latch and Check Bit Input

Latch are latched to their previous state when LOW. When HIGH, the Data Input Latch and Check Bit Input Latch

follow the input data and input check bits.

GENERATE

A multifunction pin which, when LOW, is in the Check Bit Generate Mode. In this mode, the device generates the

check bits or GENERATE partial check bits specific to the data in the Data Input Latch. The generated check bits

are placed on the SC outputs. Also, when LOW, the Data Out Latch is latched to its previous state.

When HIGH, the device is in the Detect or Correct Mode. In this mode, the device detects single and multiple

errors and generates syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch.

In the Correct Mode, single bit errors are also automatically corrected and the corrected data is placed at the

inputs of the Data Output Latch. The syndrome result is placed on the SC outputs and indicates in a coded form

the number of errors and the specific bit-in-error. When HIGH, the Data Output Latch follows the output of the

Data Input Latch as modified by the correction logic network. In Correct Mode, single bit errors are corrected by

the network before being loaded into the Data Output Latch. In Detect Mode, the contents of the Data Input Latch

are passed through the correction network unchanged into the Data Output Latch.

The Data Output Latch is

disabled, with its contents unchanged, if the EDC is in the Generate Mode.

O

Syndrome Check Bit outputs. Eight outputs which hold the check bits and partial check bits when the EDC is in

the Generate Mode and will hold the syndrome/partial syndrome bits when the device is in the Detect or Correct

modes. All are 3-state outputs.

I

Output Enable—Syndrome Check Bits. In the HIGH condition, the SC outputs are in the high impedance state.

When LOW, all SC output lines are enabled.

ERROR

O

In the Detect or Correct Mode, this output will go LOW if one or more data or check bits contain an error. When

HIGH, no errors have been detected. This pin is forced HIGH in the Generate Mode.

MULT

ERROR

O

In the Detect or Correct Mode, this output will go LOW if two or more bit errors have been detected. A HIGH level

indicates that either one or no errors have been detected. This pin is forced HIGH in the Generate Mode.

CORRECT

I

The correct input which, when HIGH, allows the correction network to correct any single-bit error in the Data Input

Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the device will

drive data directly from the Data Input Latch to the Data Output Latch without correction.

I

Output Enable—Bytes 0, 1, 2, 3. Data Output Latch. Control the three-state output buffers for each of the four

bytes of the Data Output Latch. When LOW, they enable the output buffer of the Data Output Latch. When HIGH,

they force the Data Output Latch buffer into the high impedance mode. One byte of the Data Output Latch is

easily activated by separately selecting the four enable lines.

DIAG

I

Select the proper diagnostic mode. They control the initialization, diagnostic and normal operation of the EDC.

I

These two code identification inputs identify the size of the total data word to be processed. The two allowable

data word sizes are 32 and 64 bits and their respective modified Hamming Codes are designated 32/39 and

and CORRECT are to be taken from the Diagnostic Latch rather than from the input control lines.

I

This is the Latch Enable for the Diagnostic Latch. When HIGH, the Diagnostic Latch follows the 32-bit data on the

input lines. When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic

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