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IDT70V05S Datasheet(PDF) 13 Page - Integrated Device Technology

Part # IDT70V05S
Description  HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70V05S Datasheet(HTML) 13 Page - Integrated Device Technology

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IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
6.35
13
TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION
Inputs
Outputs
A0L-A12L
CE
CE
CE
CE
CEL
CE
CE
CE
CE
CER A0R-A12R BUSY
BUSY
BUSY
BUSY
BUSYL
(1)
BUSY
BUSY
BUSY
BUSY
BUSYR
(1)
Function
XX
NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
LL
MATCH
(2)
(2)
Write Inhibit
(3)
NOTES:
2941 tbl 16
1. Pins
BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT70V05 are push pull, not open drain outputs. On slaves the
BUSYX input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after
the address and enable inputs of this port. If tAPS is not met, either
BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when
BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when
BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
2941 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
The IDT70V05 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT70V05 has an
automatic power down feature controlled by
CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(
CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each port.
The left port interrupt flag (
INTL) is set when the right port
writes to memory location 1FFE (HEX). The left port clears the
interrupt by reading address location 1FFE. Likewise, the
right port interrupt flag (
INTR) is set when the left port writes to
memory location 1FFF (HEX) and to clear the interrupt flag
(
INTR), the right port must read the memory location 1FFF.
The message (8 bits) at 1FFE or 1FFF is user-defined. If the
interrupt function is not used, address locations 1FFE and
1FFF are not used as mail boxes, but as part of the random
access memory. Refer to Truth Table for the interrupt opera-
tion.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signals the other side that the RAM is “Busy”. The busy pin can
then be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an


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