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IDT70V05S Datasheet(PDF) 9 Page - Integrated Device Technology

Part # IDT70V05S
Description  HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70V05S Datasheet(HTML) 9 Page - Integrated Device Technology

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IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
6.35
9
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
NOTES:
1.
CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
SEM"A"
2941 drw 12
tSPS
MATCH
R/
W"A"
MATCH
A0"A"-A2"A"
SIDE
“A”
(2)
SEM"B"
R/
W"B"
A0"B"-A2"B"
SIDE
(2)
“B”
NOTES:
1. DOR = DOL = VIL,
CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3.
This parameter is measured from R/
WA or SEMA going high to R/WB or SEMB going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
SEM
2941 drw 11
tAW
tEW
tSOP
I/O0
VALID ADDRESS
tSAA
R/
W
tWR
tOH
tACE
VALID ADDRESS
DATAIN
VALID
DATAOUT
tDW
tWP
tDH
tAS
tSWRD
tAOE
Read Cycle
Write Cycle
A0-A2
OE
VALID(2)


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