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IDT70121L25J Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT70121L25J Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 12 page 6.10 6 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) 70121X25 70121X35 70121X45 70121X55 70125X25 70125X35 70125X45 70125X55 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time (3) 25 — 35 — 45 — 55 — ns tEW Chip Enable to End-of-Write 20 — 30 — 35 — 40 — ns tAW Address Valid to End-of-Write 20 — 30 — 35 — 40 — ns tAS Address Set-up Time 0 — 0 — 0 — 0 — ns tWP Write Pulse Width (6) 20 — 30 — 35 — 40 — ns tWR Write Recovery Time 0 — 0 — 0 — 0 — ns tDW Data Valid to End-of-Write 12 — 20 — 20 — 20 — ns tHZ Output High-Z Time (1,2) —10 — 15 —20 — 30 ns tDH Data Hold Time (5) 0— 0 — 0— 0 — ns tWZ Write Enabled to Output in High-Z (1,2) —10 — 15 —20 — 30 ns tOW Output Active from End-of-Write (1,2) 0— 0 — 0— 0 — ns NOTES: 2654 tbl 09 1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/ W = VIL must occur after tBAA . 4. “X” in part numbers indicates power rating (S or L). 5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions.Although tDH and tow values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW. 6. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/ W W W W W CONTROLLED TIMING(1,5,8) R/ W tWC tHZ tAW tHZ tAS tWP DATAOUT tDW tDH tOW OE ADDRESS DATAIN CE tWZ (4) (4) tWR 2654 drw 07 (3) (7) (2) (6) (7) (7) NOTES: 1. R/ W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL 3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal ( CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. |
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