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IDT7015S Datasheet(PDF) 13 Page - Integrated Device Technology

Part No. IDT7015S
Description  HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
Download  20 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7015S Datasheet(HTML) 13 Page - Integrated Device Technology

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IDT7015S/L
HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.12
13
TIMING WAVEFORM OF READ WITH
BUSY
BUSY
BUSY
BUSY
BUSY (M/SSSSS = VIH)(2,4,5)
2954 drw 13
tDW
tAPS
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
(1)
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD (3)
tWDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/
S=VIL.
2.
CEL = CER = VIL.
3.
OE = VIL for the reading port.
4. If M/
S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH
BUSY
BUSY
BUSY
BUSY
BUSY
2954 drw 14
R/
W"A"
BUSY"B"
tWP
tWB
R/
W"B"
tWH
(1)
(2)
NOTES:
1. tWH must be met for both
BUSY input (SLAVE) and output (MASTER).
2.
BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".


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