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IDT7015S Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDT7015S
Description  HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM
Download  20 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7015S Datasheet(HTML) 1 Page - Integrated Device Technology

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FUNCTIONAL BLOCK DIAGRAM
• Interrupt and Busy Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• TTL-compatible, single 5V (
±10%) power supply
• Available in ceramic 68-pin PGA, 68-pin PLCC, and an
80-pin TQFP
• Industrial temperature range (–40
°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7015 is a high-speed 8K x 9 Dual-Port Static
RAMs. The IDT7015 is designed to be used as stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 18-bit-or-more word systems. Using the IDT
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35ns (max.)
— Commercial: 12/15/17/20/25/35ns (max.)
• Low-power operation
— IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7015 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading
more than one device
•M/
S = H for BUSY output flag on Master
M/
S = L for BUSY input on Slave
Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2954/2
HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
IDT7015S/L
NOTES:
1. In MASTER mode:
BUSY is an output and is a push-pull driver
In SLAVE mode:
BUSY is input.
2.
BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.12
1
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
WL
CEL
OEL
BUSYL
A12L
A0L
2954 drw 01
I/O0L- I/O8L
CEL
OEL
R/
WL
SEML
INTL
M/
S
BUSYR
I/O0R-I/O8R
A12R
A0R
SEMR
INTR
CER
OER
(2)
(1,2)
(1,2)
(2)
R/
WR
CER
OER
R/
WR
13
13
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.


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